Extensible iterative multiplier

Patent metadata

Field	Value
Publication number	US-9563401-B2
Application number	US-201314099949-A
Country	US
Kind code	B2
Filing date	Dec 7, 2013
Priority date	Dec 7, 2012
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

An extensible iterative multiplier design is provided. Embodiments provide cascaded 8-bit multipliers for simplifying the performance of multi-byte multiplications. Booth encoding is performed in the lowest order multiplier, with the result of the Booth encoding then provided to higher order multipliers. Additionally, multiply-add operations can be performed by initializing a partial product sum register. Configurable connections between the multipliers facilitate a variety of possible multiplication options, including the possibility of varying the width of the operands.

First claim

What is claimed is:

1. An apparatus for mathematical manipulation comprising:
a first multiplier logic which can multiply two binary numbers of a first width;
a second multiplier logic which can multiply two binary numbers of a second width; and
a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.

2. The apparatus of claim 1 wherein the first multiplier and the second multiplier include configuration logic comprising a partial product register of the third width.

3. The apparatus of claim 2 wherein the partial product register is initialized to a value in order to accomplish a multiply-accumulate operation.

4. The apparatus of claim 1 wherein the first multiplier and the second multiplier include configuration logic comprising a carry-save adder having a width value of the third width plus two.

5. The apparatus of claim 1 wherein the first multiplier provides Booth encoding.

6. The apparatus of claim 1 wherein the first width and the second width are the same.

7. The apparatus of claim 6 wherein the first width and the second width are each eight bits.

8. The apparatus of claim 7 further comprising a third multiplier and a fourth multiplier connected to the first multiplier and the second multiplier, wherein the third multiplier and the fourth multiplier each multiply eight bits.

9. The apparatus of claim 8 further comprising added configuration logic wherein the first multiplier, the second multiplier, the third multiplier, and the fourth multiplier are configured to multiply two 32-bit binary numbers.

10. The apparatus of claim 9 wherein the two 32-bit binary numbers are multiplied in 16 iterations.

11. The apparatus of claim 8 wherein the multiplication by the first multiplier is by iteration and wherein the iteration includes four steps to accomplish eight-bit multiplication.

12. The apparatus of claim 11 wherein a 10-bit addend is generated and a carry-save addition is performed with a stored partial product.

13. The apparatus of claim 11 wherein eight upper bits from the multiplication are stored in carry-save form.

14. The apparatus of claim 1 wherein the multiplication, that is accomplished iteratively, involves cascading a Booth-encoded signal from the first multiplier to the second multiplier.

15. The apparatus of claim 1 further comprising a register for a multiplier number and register for a multiplicand number.

16. The apparatus of claim 15 wherein the register, for the multiplier number, is shifted to produce a Booth encoding.

17. A method of logical calculation comprising:
configuring a first multiplier logic which can multiply two binary numbers of a first width and a second multiplier logic which can multiply two binary numbers of a second width through a connection between the first multiplier logic and the second multiplier logic to enable multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.

18. A computer implemented method for implementation of a logical calculation apparatus comprising:
implementing a first multiplier logic which can multiply two binary numbers of a first width;
implementing a second multiplier logic which can multiply two binary numbers of a second width; and
implementing a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.

19. A computer program product embodied in a non-transitory computer readable medium for implementation of a logical calculation apparatus comprising code which causes one or more processors to perform operations of:
implementing a first multiplier logic which can multiply two binary numbers of a first width;
implementing a second multiplier logic which can multiply two binary numbers of a second width; and
implementing a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.

20. A computer system for implementation of a logical calculation apparatus comprising:
a memory which stores instructions;
one or more processors coupled to the memory wherein the one or more processors are configured to:
implement a first multiplier logic which can multiply two binary numbers of a first width;
implement a second multiplier logic which can multiply two binary numbers of a second width; and
implement a connection between the first multiplier logic and the second multiplier logic that enables multiplication of two binary numbers of a third width where the third width has a width that is a sum of the first width and the second width, wherein the multiplication of the two binary numbers of the third width is accomplished iteratively, and wherein an opcode is used to configure the first multiplier logic and the second multiplier logic to enable the multiplication of the two binary numbers of the third width.

Assignees

• Wave Semiconductor Inc
• Wave Computing Inc

Inventors

• Chaudhuri Samit
• Danilak Radoslav

Classifications

• G06F7/5338

  each bitgroup having two new bits, e.g. 2nd order MBA · CPC title

• G06F7/5324 Primary

  partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers · CPC title