Multiplication circuitry, apparatus, system, chip-containing product, method and computer-readable medium
US-2024329932-A1 · Oct 3, 2024 · US
each bitgroup having two new bits, e.g. 2nd order MBA
each bitgroup having two new bits, e.g. 2nd order MBA · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/5338 |
| Official title | {each bitgroup having two new bits, e.g. 2nd order MBA} |
| Display label | each bitgroup having two new bits, e.g. 2nd order MBA |
| Total patents | 37 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is declining.
| Year | Patents |
|---|---|
| 2015 | 6 |
| 2016 | 4 |
| 2017 | 5 |
| 2018 | 4 |
| 2019 | 3 |
| 2020 | 5 |
| 2021 | 6 |
| 2022 | 2 |
| 2024 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Commutative 1ulp hardware multiplier
US-2024311083-A1 · Sep 19, 2024 · US
Full adder cell with improved power efficiency
US-11294631-B2 · Apr 5, 2022 · US
Method and apparatus for performing deep learning operations
US-2022035629-A1 · Feb 3, 2022 · US
Full adder cell with improved power efficiency
US-11169779-B2 · Nov 9, 2021 · US
Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US-11163720-B2 · Nov 2, 2021 · US
Full adder cell with improved power efficiency
US-2021124558-A1 · Apr 29, 2021 · US
Full adder cell with improved power efficiency
US-2021124559-A1 · Apr 29, 2021 · US
Programmable multiply-add array hardware
US-10970043-B2 · Apr 6, 2021 · US
Massively parallel, associative multiplier accumulator
US-10891991-B2 · Jan 12, 2021 · US
Programmable multiply-add array hardware
US-2020293283-A1 · Sep 17, 2020 · US
Programmable multiply-add array hardware
US-10678507-B2 · Jun 9, 2020 · US
Massively parallel, associative multiplier-accumulator
US-2020168257-A1 · May 28, 2020 · US
Processing circuitry
US-10649732-B2 · May 12, 2020 · US
Processing circuitry
US-2020042288-A1 · Feb 6, 2020 · US
Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US-2019227982-A1 · Jul 25, 2019 · US
Programmable multiply-add array hardware
US-2019196788-A1 · Jun 27, 2019 · US
Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US-10289605-B2 · May 14, 2019 · US
Apparatus and method for processing an instruction matrix specifying parallel and dependent operations
US-2018137081-A1 · May 17, 2018 · US
Binary fused multiply-add floating-point calculations
US-9959093-B2 · May 1, 2018 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/5338?
- CPC G06F7/5338 is the Cooperative Patent Classification code for “each bitgroup having two new bits, e.g. 2nd order MBA.”
- How many patents are filed under CPC G06F7/5338 (each bitgroup having two new bits, e.g. 2nd order MBA)?
- Our database includes 37 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/5338 growing?
- Publication counts under this code: 2 in 2022 vs 2 in 2024 (latest complete years).