Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry

Patent metadata

Field	Value
Publication number	US-9558545-B2
Application number	US-201514730997-A
Country	US
Kind code	B2
Filing date	Jun 4, 2015
Priority date	Dec 3, 2014
Publication date	Jan 31, 2017
Grant date	Jan 31, 2017

Abstract

Systems and methods for predicting and controlling pattern quality data (e.g., critical dimension and/or pattern defectivity) in patterned wafers using patterned wafer geometry (PWG) measurements are disclosed. Correlations between PWG measurements and pattern quality data measurements may be established, and the established correlations may be utilized to provide pattern quality data predictions for a given wafer based on geometry measurements obtained for the give wafer. The predictions produced may be provided to a lithography tool, which may utilize the predictions to correct focus and/or title errors that may occur during the lithography process.

First claim

What is claimed is:

1. A method, comprising:
obtaining pattern quality data for at least one reference wafer;
generating at least one pattern quality binary map for the at least one reference wafer;
obtaining patterned wafer geometry data for the at least one reference wafer;
generating at least one patterned wafer geometry binary map for the at least one reference wafer based on at least one threshold;
selecting a threshold among the at least one threshold, the selected threshold providing a best matching between the at least one patterned wafer geometry binary map and the at least one pattern quality binary map; and
providing a pattern quality data prediction for a new wafer based on the selected threshold.

2. The method of claim 1 , wherein said providing a pattern quality data prediction for a new wafer based on the selected threshold further comprises:
obtaining patterned wafer geometry data for the new wafer;
generating a patterned wafer geometry binary map for the new wafer based on the selected threshold; and
providing a predicted pattern quality binary map for the new wafer based on the patterned wafer geometry binary map.

3. The method of claim 1 , wherein the pattern quality data includes at least one of: a critical dimension measurement and a pattern defect measurement.

4. The method of claim 1 , wherein said generating at least one pattern quality binary map for the at least one reference wafer further comprises:
dividing the at least one reference wafer into a plurality of pattern quality measurement sites; and
indicating whether the pattern quality data within the plurality of pattern quality measurement sites is acceptable or unacceptable.

5. The method of claim 4 , wherein said generating at least one patterned wafer geometry binary map for the at least one reference wafer based on at least one threshold further comprises:
dividing the at least one reference wafer into a plurality of patterned wafer geometry measurement sites; and
indicating whether the pattern quality data within the plurality of measurement sites is below or above the at least one threshold.

6. The method of claim 5 , wherein the plurality of pattern quality measurement sites and the plurality of patterned wafer geometry measurement sites are substantially similar.

7. The method of claim 1 , wherein the pattern quality data prediction for the new wafer is provided prior to the new wafer undergoing a lithography process.

8. The method of claim 7 , further comprising:
preventing the new wafer from entering the lithography process when the pattern quality data prediction for the new wafer is predicted to be unacceptable.

9. The method of claim 7 , further comprising:
calculating at least one of a focus correctable and a tilt correctable for the new wafer; and
providing the at least one of a focus correctable and a tilt correctable to the lithography process for correction of at least one of a focus error and a title error during the lithography process.

10. A system, the system comprising:
an imaging device configured to obtain pattern quality data and patterned wafer geometry data for at least one reference wafer; and
a processor in communication with the imaging device, the processor configured to:
generate at least one pattern quality binary map for the at least one reference wafer;
generate at least one patterned wafer geometry binary map for the at least one reference wafer based on at least one threshold;
select a threshold among the at least one threshold, wherein the selected threshold provides a best matching between the at least one patterned wafer geometry binary map and the at least one pattern quality binary map; and
provide a pattern quality data prediction for a new wafer based on the selected threshold.

11. The system of claim 10 , wherein the imaging device is further configured obtain patterned wafer geometry data for the new wafer, and wherein the processor is further configured to generate a patterned wafer geometry binary map for the new wafer based on the selected threshold and provide a predicted pattern quality binary map for the new wafer based on the patterned wafer geometry binary map.

12. The system of claim 10 , wherein the pattern quality data includes at least one of: a critical dimension measurement and a pattern defect measurement.

13. The system of claim 10 , wherein the processor generates the at least one pattern quality binary map for the at least one reference wafer by dividing the at least one reference wafer into a plurality of pattern quality measurement sites and indicating whether the pattern quality data within the plurality of pattern quality measurement sites is acceptable or unacceptable.

14. The system of claim 13 , wherein the processor generates the at least one patterned wafer geometry binary map for the at least one reference wafer by dividing the at least one reference wafer into a plurality of patterned wafer geometry measurement sites and indicating whether the pattern quality data within the plurality of measurement sites is below or above the at least one threshold.

15. The system of claim 14 , wherein the plurality of pattern quality measurement sites and the plurality of patterned wafer geometry measurement sites are substantially similar.

16. The system of claim 10 , wherein the processor provides the pattern quality data prediction for the new wafer prior to the new wafer undergoing a lithography process.

17. The system of claim 16 , wherein the processor is further configured to prevent the new wafer from entering the lithography process when the pattern quality data prediction for the new wafer is predicted to be unacceptable.

18. The system of claim 16 , wherein the processor is further configured to calculate at least one of a focus correctable and a tilt correctable for the new wafer, and provide the at least one of a focus correctable and a tilt correctable to the lithography process for correction of at least one of a focus error and a title error during the lithography process.

19. A method, comprising:
obtaining critical dimension measurements for a reference wafer at a plurality of critical dimension measurement sites;
generating a critical dimension binary map for the reference wafer, wherein the a critical dimension binary map indicates whether the critical dimension within the plurality of critical dimension measurement sites is acceptable or unacceptable;
obtaining patterned wafer geometry measurements for the reference wafer at a plurality of patterned wafer geometry measurement sites;
generating at least one patterned wafer geometry binary map for the reference wafer based on at least one threshold;
selecting a threshold among the at least one threshold responsible for generating a best matching patterned wafer geometry binary map against the critical dimension binary map; and
providing a critical dimension prediction for a new wafer based on the selected threshold.

20. The method of claim 19 , wherein said providing a critical dimension prediction for a new wafer based on the selected threshold further comprises:
obtaining patterned wafer geometry data for the new wafer;
generating a patterned wafer geometry binary map for the new wafer based on the selected threshold; and
providing a predicted critical dimension binary map for the new wafer based on the patterned wafer geometry binary map.

21. A method, comprising:
obtaining pattern defect measurements for a reference wafer at a plurality of pa

Assignees

• Kla Tencor Corp

Inventors

• Vukkadala Pradeep
• Veeraraghavan Sathish
• Dey Soham
• Sinha Jaydeep

Classifications

• H10P74/203

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• G06T7/001 Primary

  using an image reference approach · CPC title

• G06T7/0004 Primary

  Industrial image inspection · CPC title

• G06F18/22

  Matching criteria, e.g. proximity measures · CPC title