Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Patent metadata

Field	Value
Publication number	US-9543935-B1
Application number	US-201514794235-A
Country	US
Kind code	B1
Filing date	Jul 8, 2015
Priority date	Jul 8, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Embodiments relate to programmable delay circuit. An aspect includes a first stage comprising a first hybrid fin field effect transistor (finFET) comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins. Another aspect includes a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins.

First claim

What is claimed is:

1. A programmable delay circuit, comprising:
a first stage comprising a first hybrid fin field effect transistor (finFET), the first hybrid finFET comprising a first gate corresponding to a first control FET, and a second gate corresponding to a first default FET, and a first plurality of fins, wherein the first gate and the second gate of the first stage each partially control a first shared fin of the first plurality of fins; and
a second stage connected in series with the first stage, the second stage comprising a second hybrid finFET, the second hybrid finFET comprising a first gate corresponding to a second control FET, and a second gate corresponding to a second default FET, and a second plurality of fins, wherein the first gate and the second gate of the second stage each partially control a second shared fin of the second plurality of fins,
wherein the first default FET and the second default FET each receive a gate voltage from a power supply rail of the programmable delay circuit.

2. The programmable delay circuit of claim 1 , wherein the first default FET and the first control FET are in parallel in the first hybrid finFET, and wherein the second default FET and the second control FET are in parallel in the second hybrid finFET.

3. The programmable delay circuit of claim 1 , wherein the first control FET receives a first control signal as a gate voltage, and the second control FET receives a second control signal as a gate voltage.

4. The programmable delay circuit of claim 3 , further comprising an input/output FET that is connected in series with the first stage and the second stage, wherein the input/output FET receives an input signal, and outputs an output signal having a specified delay based on the first control signal and the second control signal.

5. The programmable delay circuit of claim 4 , wherein the input/output FET comprises a trigate finFET comprising three fins.

6. The programmable delay circuit of claim 5 , wherein the first plurality of fins and the second plurality of fins each comprise three fins that correspond to the three fins of the trigate finFET.

7. The programmable delay circuit of claim 6 , wherein the three fins of the input/output FET are located between an output node and a first source/drain connection; wherein the three fins of the first hybrid finFET are located between the first source/drain connection and a second source/drain connection, and wherein the three fins of the second hybrid finFET is located between the second source/drain connection and a ground node.

8. The programmable delay circuit of claim 1 , wherein the first control FET exclusively controls at least two fins of the first plurality of fins, and wherein the second control FET exclusively controls at least two fins of the second plurality of fins.

9. The programmable delay circuit of claim 1 , wherein the first plurality of fins and the second plurality of fins each comprise 3-dimensional silicon fins.

Assignees

• IBM

Inventors

• Ankenapalli Vijay K
• Datta Ayan
• George Sumitha
• Nagarajan Charudhattan
• Warnock James D

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H03K5/134 Primary

  with field-effect transistors · CPC title

• H01L27/0886

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title

• H10D84/0158

  the components including FinFETs · CPC title