Variable delay element

Patent metadata

Field	Value
Publication number	US-9432008-B2
Application number	US-201414337896-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Jul 24, 2013
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A delay circuit includes first and second transistors and a biasing circuit. The first transistor has a control node coupled to an input node of the delay circuit, a first main current node coupled to a first supply voltage, and a second main current node coupled to an output node of the delay circuit. A second transistor has a control node coupled to the input node, a first main current node coupled to a second supply voltage, and a second main current node coupled to the output node. The biasing circuit is configured to generate first and second differential control voltages, to apply the first differential control voltage to a further control node of the first transistor and to apply the second differential control voltage to a further control node of the second transistor.

First claim

What is claimed is:

1. A delay circuit comprising:
an input node;
an output node;
a first transistor of a first conductivity type, the first transistor having a control node coupled to the input node, a first main current node coupled to a first supply voltage node, and a second main current node coupled to the output node through a third transistor;
a second transistor of a second conductivity type, the second transistor having a control node coupled to the input node, a first main current node coupled to a second supply voltage node, and a second main current node coupled to the output node through a fourth transistor;
the third transistor having the first conductivity type and having a control node, wherein the first main current node of the first transistor is coupled to the first supply voltage node via the third transistor;
the fourth transistor having the second conductivity type and having a control node, wherein the first main current node of the second transistor is coupled to the second supply voltage node via the fourth transistor; and
a biasing circuit having a first differential control voltage output coupled to a further control node of the first transistor and a second differential control voltage output coupled to a further control node of the second transistor.

2. The delay circuit of claim 1 , wherein the biasing circuit is configured to adjust a delay of the delay circuit by modifying voltage levels of the first and second differential control voltages.

3. The delay circuit of claim 1 , wherein the biasing circuit comprises a differential amplifier.

4. The delay circuit of claim 1 , further comprising a control circuit coupled to a control input of the biasing circuit to provide a control signal to the biasing circuit to control levels of the first and second differential control voltages based on a delay to be applied by the delay circuit.

5. The delay circuit of claim 1 , wherein the first and second transistors each comprise an SOI (semiconductor on insulator) structure and wherein the further control nodes are coupled to back gates of the first and second transistors.

6. The delay circuit of claim 5 , wherein the first and second transistors each comprise a semiconductor layer isolated from the back gate of the respective transistor by a layer of insulator.

7. The delay circuit of claim 5 , wherein the first transistor comprises a p-type well forming the back gate and wherein the p-type well is isolated from a p-type substrate by a deep n-type well.

8. The delay circuit of claim 1 , wherein the first differential control voltage output of the biasing circuit is coupled to a further control node of the third transistor and wherein the second differential control voltage output of the biasing circuit is coupled to a further control node of the fourth transistor.

9. The delay circuit of claim 1 , wherein the control node of the third transistor is coupled to the input node and wherein the control node of the fourth transistor is coupled to the input node.

10. The delay circuit of claim 1 , wherein the control node of the third transistor is coupled to receive a third control voltage and the control node of the fourth transistor is coupled to receive a fourth control voltage.

11. An electronic device comprising:
the delay circuit of claim 1 ; and
circuitry coupled to the output node of the delay circuit.

12. The electronic device of claim 11 , wherein the circuitry provides a feedback signal to the biasing circuit.

13. A delay circuit comprising:
an input node;
an output node;
a p-type silicon on insulator (SOI) transistor having a gate coupled to the input node, a first source/drain region coupled to a first supply voltage node, and a second source/drain region coupled to the output node;
an n-type SOI transistor having a gate coupled to the input node, a first source/drain region coupled to a second supply voltage node, and a second source/drain region coupled to the output node; and
a biasing circuit having a first delay control output coupled to a back gate of the p-type SOI transistor and a second delay control output coupled to a back gate of the n-type SOI transistor;
wherein the first source/drain region and the second source/drain region of the n-type SOI transistor are separated by a channel region;
wherein the first source/drain region, the second source/drain region, and the channel region of the n-type SOI transistor are disposed on an oxide layer;
wherein the oxide layer is disposed on a p-type well that forms the back gate of the n-type SOI transistor;
wherein the p-type well is disposed in an n-type well; and
wherein the n-type well is disposed in a substrate.

14. The delay circuit of claim 13 , wherein the biasing circuit comprises a differential amplifier.

15. The delay circuit of claim 13 , further comprising a control circuit coupled to a control input of the biasing circuit to provide a control signal to the biasing circuit to control levels of signals provided at the first and second delay control outputs.

16. The delay circuit of claim 13 , further comprising:
a second p-type transistor having a control node, wherein the first source/drain region of the second p-type transistor is coupled to the first supply voltage node via the second p-type transistor; and
a second n-type transistor a control node, wherein the first source/drain region of the second n-type transistor is coupled to the second supply voltage node via the second n-type transistor.

17. The delay circuit of claim 16 , wherein the second p-type transistor comprises an SOI transistor;
wherein the first delay control output of the biasing circuit is coupled to a back gate of the second p-type transistor;
wherein the second n-type transistor comprises an SOI transistor; and
wherein the second delay control output of the biasing circuit is coupled to a back gate of the second n-type transistor.

18. The delay circuit of claim 16 , wherein the control node of the second p-type transistor is coupled to the input node and the control node of the second n-type transistor is coupled to the input node.

19. The delay circuit of claim 16 , wherein the control node of the second p-type transistor is coupled to receive a third control voltage and the control node of the second n-type transistor is coupled to receive a fourth control voltage.

20. A method of operating a delay circuit, the method comprising:
generating first and second differential control voltages;
applying the first differential control voltage to a further control node of a first transistor and further control node of a third transistor having a first conductivity type, the first transistor and the third transistor having control nodes coupled to an input node of the delay circuit, a first main current node of the first transistor coupled to a first supply voltage, and a second main current node of the first transistor coupled to an output node of the delay circuit through the third transistor;
applying the second differential control voltage to a further control node of a second transistor and a further control node of a fourth transistor having a second conductivity type, the second transistor and the fourth transistor having control nodes coupled to the input node, a first main current node of the second transistor coupled to a second supply voltage, and a second main current node of the second transistor coupled to the output node through the fourth transistor; and
applying an input signal to the input node, wherein an outpu

Assignees

• St Microelectronics Sa
• St Microelectronics Int Nv

Inventors

• LE TUAL STéPHANE
• Singh Pratap Narayan

Classifications

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K2217/0018

  Special modifications or use of the back gate voltage of a FET · CPC title

• H03K2005/00215

  where the conduction path of multiple FET's is in parallel or in series, all having the same gate control · CPC title

• H03K2005/00208

  using differential stages · CPC title

• H03K5/134 Primary

  with field-effect transistors · CPC title