Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement

Patent metadata

Field	Value
Publication number	US-9515668-B2
Application number	US-201414894483-A
Country	US
Kind code	B2
Filing date	May 31, 2014
Priority date	May 31, 2013
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

An all digital phase-locked loop (PLL) and a method of controlling the PLL is provided. The method includes the steps of receiving a reference signal (f REF ) at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to multiple tunable delay elements; receiving at the multiple tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit; providing an PLL output (f DCO ) to the TDC at least partially based on the first signal input; and generating a phase error output (Φ ERR ) based on the reference signal (f REF ) and the PLL output (f DCO ), wherein the phase error output (Φ ERR ) is provided as feedback to the controller to control the PLL output (f DCO ).

First claim

The invention claimed is:

1. A method of controlling a phase-locked loop (PLL) output using an all digital phase-locked loop (ADPLL), comprising the steps of:
receiving a reference signal at a controller and a time-to-digital converter (TDC), the controller and TDC being coupled to a plurality of tunable delay elements;
receiving at the plurality of tunable delay elements a first signal input via the controller and a pulse-width modulation (PWM) circuit;
providing an PLL output to the TDC at least partially based on the first signal input; and
generating a phase error output based on the reference signal and the PLL output, wherein the phase error output is provided as feedback to the controller to control the PLL output.

2. The method of claim 1 , wherein the plurality of tunable delay elements provide a fundamental frequency, wherein the PLL output further is based partially on the fundamental frequency or a harmonic thereof.

3. The method of claim 1 , wherein the plurality of tunable delay elements is a digitally-controlled oscillator (DCO), wherein the controller is a DCO controller.

4. The method of claim 3 , wherein the plurality of tunable delay elements is a multi-stage ring DCO.

5. The method of claim 1 , further comprising receiving at the plurality of tunable delay elements a second signal input via the controller.

6. The method of claim 5 , wherein the second signal input includes one of a coarse resolution adjustment or a fine resolution adjustment, wherein the first signal input includes an ultra-fine resolution adjustment from the controller.

7. The method of claim 6 , further comprising sending ultra-fine bit data from the controller to the PWM circuit and sending coarse bit data, fine bit data, or both from the controller to the plurality of tunable delay elements.

8. The method of claim 1 , wherein at least the first signal input is synchronous with the PLL output.

9. A method of developing a System-on-a-Chip (SoC), comprising the steps of:
receiving from a user instructions in a hardware description language (HDL) at a silicon compiler, wherein the instructions define an all digital phase-locked loop (ADPLL);
compiling the instructions; and
constructing the SoC having the ADPLL defined by the instructions, wherein the ADPLL comprises:
a plurality of tunable delay elements;
a controller; and
a pulse-width modulation (PWM) circuit,
wherein the controller is configured to:
provide a first resolution adjustment signal to the PWM circuit, which PWM circuit is configured to provide a first input signal to the plurality of delay elements based on the first resolution adjustment signal and the current output of the plurality of tunable delay elements;
receive a phase error output that is based on a reference signal and the current output of the plurality of tunable delay elements; and
alter the first resolution adjustment signal based on the phase error output.

10. The method of claim 9 , wherein the plurality of tunable delay elements is one of a digitally-controlled oscillator (DCO) or a delay-locked loop (DLL) circuit.

11. The method of claim 9 , wherein the controller is further configured to provide a second resolution adjustment signal to the plurality of delay elements that affects the current output of the plurality of tunable delay elements.

12. The method of claim 11 , wherein the controller is further configured to receive the first resolution adjustment signal and the second resolution adjustment signal severally or simultaneously.

13. The method of claim 9 , further comprising storing the instructions in a digital cell library.

14. The method of claim 9 , wherein the provided SoC further comprises both digital and analog cells.

Assignees

• Univ Michigan Regents

Inventors

• Faisal Muhammad
• Wentzloff David D

Classifications

• H03L7/0997 Primary

  Controlling the number of delay elements connected in series in the ring oscillator · CPC title

• H03K5/134 Primary

  with field-effect transistors · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/103

  the additional signal being a digital signal · CPC title

• H03L2207/06

  Phase locked loops with a controlled oscillator having at least two frequency control terminals · CPC title