Static timing analysis (STA) using derived boundary timing constraints for out-of-context (OOC) hierarchical entity analysis and abstraction

Patent metadata

Field	Value
Publication number	US-9542524-B2
Application number	US-201514606053-A
Country	US
Kind code	B2
Filing date	Jan 27, 2015
Priority date	Jan 27, 2015
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

First claim

What is claimed is:

1. A system for performing a static timing analysis, said system comprising:
a memory storing an integrated circuit design partitioned into multiple hierarchical entities; and,
at least one processor accessing said memory and identifying multiple signal pathways within a hierarchical entity selected for analysis from said multiple hierarchical entities,
said multiple signal pathways identified by said processor comprising at least a first signal pathway, and
said at least one processor further performing the following:
determining an internal timing constraint of a specific logic device in said first signal pathway based on a known reference value;
deriving a first boundary timing constraint associated with said first signal pathway based on said internal timing constraint;
deriving a second boundary timing constraint associated with said first signal pathway based on said first boundary timing constraint and a target slack value for said internal timing constraint, said first boundary timing constraint and said second boundary timing constraint are boundaries of valid timing signals for said hierarchical entity;
performing a static timing analysis of said hierarchical entity using said second boundary timing constraint;
making design adjustments to said hierarchical entity based on results of said static timing analysis;
iteratively repeating said determining of said internal timing constraint, said deriving of said first boundary timing constraint, said deriving of said second boundary timing constraint, said performing of said static timing analysis, and said making of said design adjustments in order to minimize overlap between victim and aggressor timing windows prior to generating an overall signal timing model for said integrated circuit design; and
generating a timing abstraction for said hierarchical entity based on said static timing analysis, multiple ones of said timing abstraction being used to generate said overall signal timing model for said integrated circuit design.

2. The system of claim 1 , said at least one processor further generating said overall signal timing model for said integrated circuit design using said timing abstraction for said hierarchical entity and other timing abstractions generated for other hierarchical entities within said integrated circuit design.

3. The system of claim 2 , said multiple signal pathways identified by said processor further comprising a second signal pathway adjacent to said first signal pathway within said hierarchical entity and said static timing analysis taking into consideration noise coupling between said first signal pathway and said second signal pathway.

4. The system of claim 3 ,
said specific logic device comprising an initial storage element within said first signal pathway,
said first signal pathway comprising an aggressor signal pathway between a primary input and said specific logic device, and
said second signal pathway comprising a victim signal pathway.

5. The system of claim 4 ,
said memory further storing library information for logic devices in each of said hierarchical entities,
said internal timing constraint comprising a required arrival time for said specific logic device,
said known reference value being a clock arrival time,
said required arrival time for said specific logic device being determined based on said clock arrival time and a timing window for said specific logic device as indicated by said library information,
said first boundary timing constraint comprising a required arrival time for said primary input at said hierarchical entity, and
said second boundary timing constraint comprising an arrival time for said primary input at said hierarchical entity.

6. The system of claim 3 ,
said specific logic device comprising a last storage element within said first signal pathway,
said first signal pathway comprising a victim signal pathway between said specific logic device and a primary output, and
said second signal pathway comprising an aggressor signal pathway.

7. The system of claim 6 ,
said known reference value being a clock arrival time,
said internal timing constraint comprising an arrival time for said specific logic device, said arrival time for said specific logic device corresponding to said clock arrival time,
said first boundary timing constraint comprising an arrival time for said primary output at an external logic device, and
said second boundary timing constraint comprising a required arrival time for said primary output.

8. The system of claim 1 , said static timing analysis comprising any of a deterministic static timing analysis and a statistical static timing analysis.

9. The system of claim 3 , said first signal pathway and said second signal pathway being controlled by different clock signals.

10. A method of performing static timing analysis, said method comprising:
accessing a memory that stores an integrated circuit design that is partitioned into multiple hierarchical entities;
identifying multiple signal pathways in a hierarchical entity selected for analysis from amongst said multiple hierarchical entities, said multiple signal pathways comprising at least a first signal pathway;
determining an internal timing constraint of a specific logic device in said first signal pathway based on a known reference value;
deriving a first boundary timing constraint associated with said first signal pathway based on said internal timing constraint;
deriving a second boundary timing constraint associated with said first signal pathway based on said first boundary timing constraint and a target slack value for said internal timing constraint, said first boundary timing constraint and said second boundary timing constraint are boundaries of valid timing signals for said hierarchical entity;
performing a static timing analysis of said hierarchical entity using said second boundary timing constraint;
making design adjustments to said hierarchical entity based on results of said static timing analysis;
iteratively repeating said determining of said internal timing constraint, said deriving of said first boundary timing constraint, said deriving of said second boundary timing constraint, said performing of said static timing analysis, and said making of said design adjustments in order to minimize overlap between victim and aggressor timing windows prior to generating an overall signal timing model for said integrated circuit design; and
generating a timing abstraction for said hierarchical entity based on said static timing analysis, multiple ones of said timing abstraction being used to analyze said overall signal timing model for said integrated circuit design.

11. The method of claim 10 , further comprising generating said overall signal timing model for said integrated circuit design using said timing abstraction and other timing abstractions generated for other hierarchical entities within said integrated circuit design.

12. The method of claim 11 , said multiple signal pathways further comprising a second signal pathway adjacent to said first signal pathway within said hierarchical entity and said static timing analysis being performed taking into consideration noise coupling between said first signal pathway and said second signal pathway.

13. The method of claim 12 ,
said specific logic device comprising an initial storage element within said first signal pathway,
said first signal pathway comprising an aggressor signal pathway between a primary input and said specific logic device, and
said second signal pathway comprising a victim signal pathway.

14. The me

Assignees

• IBM

Inventors

• Gregerson James C
• Hathaway David J
• Kalafala Kerim
• Ko Tsz-Mei
• Rubin Alex

Classifications

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/3312 Primary

  Timing analysis · CPC title

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F17/5081 Primary

  Physics · mapped topic