CMOS compatible resonant interband tunneling cell

Patent metadata

Field	Value
Publication number	US-9536886-B2
Application number	US-201615045930-A
Country	US
Kind code	B2
Filing date	Feb 17, 2016
Priority date	Mar 2, 2015
Publication date	Jan 3, 2017
Grant date	Jan 3, 2017

Abstract

A semiconductor device includes a first diode connected transistor of a first conductivity type and a second diode connected transistor of a second conductivity type connected in series, each of the first and second diode connected transistors being configured to exhibit negative differential resistance in response to an applied voltage. The first drain and first source regions of the first diode connected transistor include dopants of the first conductivity type at degenerate dopant concentration levels and a gate of the first diode connected transistor has a work function that corresponds to that of the semiconductor containing dopants of the second conductivity type. The second drain and second source regions of the second diode connected transistor include dopants of the second conductivity type at degenerate dopant concentration levels and a gate of the second diode connected transistor has a work function that corresponds to that of the semiconductor containing dopants of the first conductivity type.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first diode connected transistor of a first conductivity type and a second diode connected transistor of a second conductivity type connected in series, each of the first and second diode connected transistors being configured to exhibit negative differential resistance in response to an applied voltage;
wherein first drain and first source regions of the first diode connected transistor comprise dopants of the first conductivity type at degenerate dopant concentration levels and a gate of the first diode connected transistor comprises dopants of the second conductivity type; and
wherein second drain and second source regions of the second diode connected transistor comprise dopants of the second conductivity type at degenerate dopant concentration levels and a gate of the second diode connected transistor comprises dopants of the first conductivity type.

2. The semiconductor device of claim 1 , wherein a channel region of the first diode connected transistor comprises dopants of the second conductivity type at a non-degenerate dopant concentration level; and
wherein a channel region of the second diode connected transistor comprises dopants of the first conductivity type at a non-degenerate dopant concentration level.

3. The semiconductor device of claim 2 , wherein the dopant concentration levels of the first drain and the first source regions and the dopant concentration levels of the second drain and the second source regions are each at least 10 19 cm −3 .

4. The semiconductor device of claim 2 , wherein the first conductivity type is n-type and the second conductivity type is p-type; and
wherein the gate of the first diode connected transistor has a work function of at least about 5.1 eV and the gate of the second diode connected transistor has a work function not greater than about 4.2 eV.

5. The semiconductor device of claim 2 , wherein the channel region of the first diode connected transistor has first deep level traps formed therein; and
wherein the channel region of the second diode connected transistor has second deep level traps formed therein.

6. The semiconductor device of claim 5 , wherein the first deep level traps are formed more proximal to the valence band edge than the conduction band edge; and
wherein the second deep level traps are formed more proximal to the conduction band edge than the valence band edge.

7. The semiconductor device of claim 2 , wherein the channel region of the first diode connected transistor and the channel region of the second diode connected transistor each comprise at least one of Si, Ge, InGaAs, C, MoS 2 , and Sn.

8. The semiconductor device of claim 1 , wherein the first diode connected transistor and the second diode connected transistor are connected at a storage node, the device further comprising:
a write field effect transistor comprising a source terminal connected to a write bit line, a gate terminal connected to a write word line, and a drain terminal connected to the storage node; and
a read field effect transistor comprising a source terminal connected to a read bit line, a gate terminal connected to the storage node, and a drain terminal connected to a read word line.

9. The semiconductor device of claim 1 , wherein the first diode connected transistor and the second diode connected transistor are connected at a storage node, the device further comprising:
a pass gate field effect transistor comprising a source terminal connected to a bit line, a gate terminal connected to a word line, and a drain terminal connected to the storage node; and
a capacitor connected to the storage node.

10. A semiconductor device comprising:
a first transistor of a first conductivity type and a second transistor of a second conductivity type connected in series, each of the first and second transistors being configured to exhibit negative differential resistance in response to an applied voltage;
wherein first drain and first source regions of the first transistor comprise dopants of the first conductivity type at degenerate dopant concentration levels and a gate of the first transistor comprises dopants of the second conductivity type; and
wherein second drain and second source regions of the second transistor comprise dopants of the second conductivity type at degenerate dopant concentration levels and a gate of the second transistor comprises dopants of the first conductivity type.

11. The semiconductor device of claim 10 , wherein the first transistor and the second transistor are connected in series between a reference voltage and a common voltage; and
wherein the reference voltage is less than a power supply voltage.

12. The semiconductor device of claim 11 , wherein the reference voltage is in a range of approximately 50 mV-200 mV.

13. The semiconductor device of claim 10 , wherein a channel region of the first transistor comprises dopants of the second conductivity type at a non-degenerate dopant concentration level; and
wherein a channel region of the second transistor comprises dopants of the first conductivity type at a non-degenerate dopant concentration level.

14. The semiconductor device of claim 13 , wherein the dopant concentration levels of the first drain and the first source regions and the dopant concentration levels of the second drain and second source regions are each at least 10 19 cm −3 .

15. The semiconductor device of claim 13 , wherein the first conductivity type is n-type and the second conductivity type is p-type; and
wherein the gate of the first transistor has a work function of at least about 5.1 eV and the gate of the second transistor has a work function not greater than about 4.2 eV.

16. The semiconductor device of claim 13 , wherein the channel region of the first transistor has first deep level traps formed therein; and
wherein the channel region of the second transistor has second deep level traps formed therein.

17. The semiconductor device of claim 16 , wherein the first deep level traps are formed more proximal to the valence band edge than the conduction band edge; and
wherein the second deep level traps are formed more proximal to the conduction band edge than the valence band edge.

18. The semiconductor device of claim 13 , wherein the channel region of the first transistor and the channel region of the second transistor each comprise at least one of Si, Ge, InGaAs, C, MoS 2 , and Sn.

19. The semiconductor device of claim 10 , wherein a gate terminal of the first transistor and a gate terminal of the second transistor are connected at a storage node and the first drain region and the second drain region are connected separately from the storage node, the device further comprising:
a write field effect transistor comprising a source terminal connected to a write bit line, a gate terminal connected to a write word line, and a drain terminal connected to the storage node; and
a read field effect transistor comprising a source terminal connected to a read bit line, a gate terminal connected to the storage node, and a drain terminal connected to a read word line.

20. The semiconductor device of claim 10 , wherein a gate terminal of the first transistor and a gate terminal of the second transistor are connected at a storage node and the first drain region and the second drain region are connected separately from the storage node, the device further comprising:
a pass gate field effect transistor comprising a source terminal connected to a bit line,

Assignees

• Bowen Christopher
• Samsung Electronics Co Ltd

Inventors

• Bowen Christopher

Classifications

• H10D89/10

  Integrated device layouts · CPC title

• H10D10/881

  Resonant tunnelling transistors · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D48/383

  Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects · CPC title

• H10D12/211

  Gated diodes · CPC title