Energy-filtered cold electron devices and methods

Patent metadata

Field	Value
Publication number	US-9704977-B2
Application number	US-201515115999-A
Country	US
Kind code	B2
Filing date	Feb 3, 2015
Priority date	Feb 4, 2014
Publication date	Jul 11, 2017
Grant date	Jul 11, 2017

Abstract

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

First claim

The invention claimed is:

1. A method for operating an energy-filtered cold electron transistor comprising the steps of:
providing the energy-filtered cold electron transistor, the energy-filtered cold electron transistor comprising a first electrode, a second electrode, a gate electrode and an electron energy filter disposed between the first electrode and the second electrode, wherein the electron energy filter comprises a quantum well;
filtering out any thermally excited electrons using the electron energy filter by a discrete state of the quantum well at room temperature;
transporting only energy-filtered cold electrons between the first and second electrodes; and
controlling the transport of the energy-filtered cold electrons using the gate electrode.

2. The method as recited in claim 1 , wherein the energy-filtered cold electron transistor comprises a sequential arrangement of the first electrode, a first tunneling barrier, a second tunneling barrier, a central island, an additional second tunneling barrier and the second electrode.

3. The method as recited in claim 2 , wherein the sequential arrangement further comprises an additional first tunneling barrier disposed between the additional second tunneling barrier and the second electrode.

4. The method as recited in claim 2 , wherein the central island is formed from a bulk semiconductor material, a semiconductor nanoparticle, a metal nanoparticle, an organic material, an inorganic material, a magnetic material, or a superconducting material.

5. The method as recited in claim 1 , wherein the electron energy filter is formed from a sequential arrangement of the first electrode, a first tunneling barrier and a second tunneling barrier.

6. The method as recited in claim 5 , wherein the quantum well is formed in the first tunneling barrier and a discrete quantum state or multiple discrete quantum states are formed in the quantum well.

7. The method as recited in claim 6 , wherein a depth of the quantum well is controlled by energy band bending of the first tunneling barrier and the energy band bending is adjusted by controlling interface charges, interface dipoles, and formation of SAMs (self-assembled monolayers) at a surface of the first tunneling barrier.

8. The method as recited in claim 1 , wherein the electron energy filter is formed from a sequential arrangement of the second electrode, an additional first tunneling barrier and an additional second tunneling barrier.

9. The method as recited in claim 8 , wherein the quantum well is formed in the additional first tunneling barrier and a discrete quantum state or multiple discrete quantum states are formed in the quantum well.

10. The method as recited in claim 9 , wherein a depth of the quantum well is controlled by energy band bending of the additional first tunneling barrier and the energy band bending is adjusted by controlling interface charges, interface dipoles, and formation of SAMs (self-assembled monolayers) at a surface of the additional first tunneling barrier.

11. The method as recited in claim 1 , wherein the energy-filtered cold electrons are produced with an effective electron temperature of 45 K or below at room temperature using the electron energy filter without any external cooling.

12. The method as recited in claim 11 , wherein the energy-filtered cold electrons produce a subthreshold swing of less than or equal to 10 mV/decade at room temperature.

13. The method as recited in claim 12 , wherein the energy-filtered cold electron transistor has a supply voltage of less than or equal to 0.1 V.

14. The method as recited in claim 1 , wherein the energy-filtered cold electron transistor comprises:
a central island disposed on an isolation layer, the central island having at least a first wall and a second wall;
a second tunneling barrier disposed on the first wall of the central island;
an additional second tunneling barrier disposed on the second wall of the central island;
a first tunneling barrier disposed on the second tunneling barrier and a first portion of the isolation layer;
an additional first tunneling barrier disposed on the additional second tunneling barrier and a second portion of the isolation layer;
the first electrode disposed on the first tunneling barrier above the first portion of the isolation layer and adjacent to the first tunneling barrier disposed on the second tunneling barrier;
the second electrode disposed on the additional first tunneling barrier above the second portion of the isolation layer and adjacent to the additional first tunneling barrier disposed on the additional second tunneling barrier;
a gate dielectric disposed above the central island; and
the gate electrode disposed on the gate dielectric.

15. The method as recited in claim 14 , wherein the gate dielectric is disposed above a portion of the first electrode, the first tunneling barrier, the second tunneling barrier, the central island, the additional second tunneling barrier, the additional first tunneling barrier and a portion of the second electrode.

16. The method as recited in claim 14 , wherein the first tunneling barrier and the second tunneling barrier are formed from a single type of material.

17. The method as recited in claim 14 , wherein the first tunneling barrier and the second tunneling barrier are formed from two different materials.

18. The method as recited in claim 14 , wherein the first electrode comprises a Cr source electrode, the first tunneling barrier comprises Cr 2 O 3 , the central island comprises Si, and the second electrode comprises a Cr drain electrode.

19. The method as recited in claim 14 , wherein the first tunneling barrier comprises Cr 2 O 3 and the second tunneling barrier comprises SiO 2 or Si 3 N 4 .

20. The method as recited in claim 14 , wherein:
the first electrode and second electrode are formed from a material selected from the group consisting of Al, Pb, Cr, Cu, Au, Ag, Pt, Pd, and Ti;
the central island is formed from a material selected from the group consisting of Si, Ge, CdSe, CdTe, GaAs, InP, InAs, Al, Pb, Cr, Cu, Au, Ag, Pt, Pd, and Ti;
the first tunneling barrier is formed from a material selected from the group consisting of Al 2 O 3 , Cr 2 O 3 , and TiO x ; and
the second tunneling barrier is formed from a material selected from the group consisting of SiO 2 , Si 3 N 4 , Al 2 O 3 , Cr 2 O 3 , and TiO x .

Assignees

• Univ Texas

Inventors

• Koh Seong Jin
• Bhadrachalam Pradeep
• Ma Liang-Chieh

Classifications

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• Y10S977/937

  Single electron transistor · CPC title

• Y10S977/774

  Exhibiting three-dimensional carrier confinement, e.g. quantum dots · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/882

  Electricity · mapped topic