Latched comparator circuit

Patent metadata

Field	Value
Publication number	US-9531352-B1
Application number	US-201514748840-A
Country	US
Kind code	B1
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Dec 27, 2016
Grant date	Dec 27, 2016

Abstract

Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair of input transistors, the first pair of transistors including gates coupled to the input nodes, a second stage including a second pair of input transistors, the second pair of transistors including gates coupled to the input nodes, and a third stage including inverters coupled to the output nodes. The inverters are coupled to the first and second stages at the same nodes to switch the output signals between different voltages based on the input signals.

First claim

What is claimed is:

1. An apparatus comprising:
input nodes to receive input signals;
output nodes to provide output signals;
a first stage including a first pair of input transistors, the first pair of input transistors including gates coupled to the input nodes;
a second stage including a second pair of input transistors, the second pair of input transistors including gates coupled to the input nodes; and
a third stage including inverters coupled to the output nodes, the inverters coupled to the first and second stages to switch the output signals between different voltages based on the input signals, the inverters including a first inverter and a second inverter, the first inverter coupled to the first and second stages at a same node of the first inverter, and the second inverter coupled to the first and second stages at a same node of the second inverter.

2. The apparatus of claim 1 , further comprising a circuit coupled to the output nodes to provide first and second additional output signals based on the output signals.

3. The apparatus of claim 2 , wherein the circuit includes a first logic gate and a second logic gate, the first logic gate including a first input coupled to a first output node of the output nodes, a second input coupled to an output of the second logic gate, and an output coupled to a first input of the second logic gate, the second logic gate including a second input coupled to a second output node of the output nodes.

4. The apparatus of claim 1 , wherein the second stage is arranged to receive a signal to deactivate the second stage.

5. The apparatus of claim 1 , wherein the input nodes, the output nodes, and the first, second, and third stages are included in a device of the apparatus, the device including memory cells and data lines coupled to the input nodes, wherein one of the input signals has a value based on a value of a selected memory cell among the memory cells.

6. An apparatus comprising:
input nodes to receive input signals;
output nodes to provide output signals;
a first stage including a first pair of input transistors, the first pair of input transistors including gates coupled to the input nodes;
a second stage including a second pair of input transistors, the second pair of input transistors including gates coupled to the input nodes; and
a third stage including inverters coupled to the output nodes, the inverters coupled to the first and second stages at same nodes to switch the output signals between different voltages based on the input signals, wherein the second stage is configured to assist the first stage to sample the input signals when a value of at least one of the input signals is less than one-half of a value of an operating voltage of the third stage.

7. The apparatus of claim 6 , wherein the second stage is configured to assist the first stage to sample the input signals when a value of at least one of the input signals is greater than one-half of a value of an operating voltage of the third stage.

8. An apparatus comprising:
a first input node and a second input node;
a first output node and a second output node;
a first plurality of transistors coupled between a first supply node and a second supply node, the first plurality of transistors including a first transistor and a second transistor coupled between the first output node and the second supply node, the first transistor coupled between the first output node and a first node, the second transistor coupled between the first node and the second supply node;
a second plurality of transistors coupled between the first and second supply nodes, the second plurality of transistors including a third transistor and a fourth transistor coupled between the second output node and the second supply node, the third transistor coupled between the second output node and a second node, the fourth transistor coupled between the second node and the second supply node;
a first input transistor coupled between the second supply node and a node between the first and second transistors, the first input transistor including a gate coupled to the first input node; and
a second input transistor coupled between the second supply node and a node between the third and fourth transistors, the second input transistor including a gate coupled to the second input node.

9. The apparatus of claim 8 , further comprising:
a third input transistor coupled between the first and second supply nodes, the third input transistor including a gate coupled to the first input node; and
a fourth input transistor coupled between the first and second supply nodes, the fourth input transistor including a gate coupled to the second input node.

10. The apparatus of claim 9 , wherein the first and second input transistors have a first transistor type and the third and fourth input transistors have a second transistor type.

11. The apparatus of claim 10 , wherein the first transistor type includes n-type and the second transistor type includes p-type.

12. The apparatus of claim 10 , wherein the first transistor type includes p-type and the second transistor type includes n-type.

13. The apparatus of claim 8 , wherein the first and second transistors of the first plurality of transistors and the third and fourth transistors of the second plurality of transistors have a same transistor type.

14. The apparatus of claim 8 , wherein at least one of the first and second input nodes is coupled to a data line associated with a memory cell.

15. A first input node and a second input node;
a first output node and a second output node;
a first plurality of transistors coupled between a first supply node and a second supply node, the first plurality of transistors including a first transistor and a second transistor coupled between the first output node and the second supply node;
a second plurality of transistors coupled between the first and second supply nodes, the second plurality of transistors including a third transistor and a fourth transistor coupled between the second output node and the second supply node;
a first input transistor coupled between the second supply node and a node between the first and second transistors, the first input transistor including a gate coupled to the first input node; and
a second input transistor coupled between the second supply node and a node between the third and fourth transistors, the second input transistor including a gate coupled to the second input node, wherein the first plurality of transistors includes a fifth transistor coupled between the first output node and the first supply node, and the second plurality of transistors includes a sixth transistor coupled between the second output node and the first supply node.

16. The apparatus of claim 15 , wherein the first plurality of transistors includes a seventh transistor coupled between the first output node and the first supply node, and the second plurality of transistors includes an eighth transistor coupled between the second output node and the first supply node.

17. An apparatus comprising:
a first node included in a first device to receive a first signal provided from a second device;
a second node included in the first device to receive a second input signal generated by the first device; and
a receiver included in the first device, the receiver including a comparator coupled to the first and second nodes, the comparator including:
output nodes to provide output signals;

a first stage including a first pair of input transistors, the first pair of input transistors including gates coupled to

Assignees

• Intel Corp

Inventors

• Aw Chee Hong

Classifications

• G11C7/1087

  Data input latches · CPC title

• H03K3/356113 Primary

  using additional transistors in the input circuit · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K3/356139 Primary

  with synchronous operation · CPC title

• G11C7/1084

  Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title