Vertical memory devices

Patent metadata

Field	Value
Publication number	US-9524983-B2
Application number	US-201614988178-A
Country	US
Kind code	B2
Filing date	Jan 5, 2016
Priority date	Mar 10, 2015
Publication date	Dec 20, 2016
Grant date	Dec 20, 2016

Abstract

A vertical memory device includes a substrate, gate lines, channels, contacts and contact spacers. The gate lines are stacked on top of each other on the substrate. The gate lines are spaced apart from each other in a vertical direction with respect to a top surface of the substrate. The gate lines include step portions that extend in a parallel direction with respect to the top surface of the substrate. The channels extend through the gate lines in the vertical direction. The contacts are on the step portions of the gate lines. The contact spacers are selectively formed along sidewalls of a portion of the contacts.

First claim

What is claimed is:

1. A vertical memory device, comprising:
a substrate;
gate lines stacked on top of each other on the substrate, the gate lines being spaced apart from each other in a vertical direction with respect to a top surface of the substrate, the gate lines including step portions that extend in a parallel direction with respect to the top surface of the substrate,
the gate lines including first gate lines and second gate lines,
wherein the first gate lines ate either on top of the second gate lines or the first gate lines are alternately stacked with the second gate lines;
channels extending through the gate lines in the vertical direction;
contacts on the step portions of the gate lines, the contacts including first contacts connected to the first gate lines and second contacts connected to the second gate lines; and
contact spacers formed along sidewalls of the first contacts,
the contact spacers not being formed along sidewalls of the second contacts.

2. The vertical memory device of claim 1 , wherein the contact spacers include one of silicon nitride and silicon oxynitride.

3. The vertical memory device of claim 2 , further comprising:
a mold protection layer covering top and lateral surfaces of the step portions, wherein
the mold protection layer includes silicon oxide.

4. The vertical memory device of claim 3 , wherein
the contact spacers surround the sidewalls of the first contacts,
the contact spacers extend through the mold protection layer,
the second contacts are in contact with the mold protection layer, and
the second contacts extend through the mold protection layer.

5. The vertical memory device of claim 1 , wherein
the substrate includes a channel region, a first region, and a second region,
the channels are on the channel region,
the first region and the second region are sequentially positioned from the channel region in the parallel direction, and
the first contacts are on the step portions included in the first region and the second contacts are on the step portions included in the second region.

6. The vertical memory device of claim 1 , wherein
the first gate lines are on top of the second gate lines,
the first gate lines include a string selection lines (SSL) and upper word lines,
the second gate lines include a ground selection line (GSL) and lower word lines,
the GSL, the lower word lines, the upper word lines, and the SSL are sequentially stacked from the top surface of the substrate, and
the first contacts are electrically connected to the SSL and the upper word lines.

7. The vertical memory device of claim 6 , wherein
the second contacts are electrically connected to the lower word lines and the GSL.

8. The vertical memory device of claim 5 , wherein
the first gate lines are on the second gate lines,
the substrate further includes a third region between the first region and the second region in the parallel direction,
the gate lines include third gate line between the first gate lines and the second gate lines, and
the contacts further include third contacts on the step portions of the third gate lines.

9. The vertical memory device of claim 1 , wherein
the first gate lines are on the second gate lines,
the gate lines include third gate lines between the first gate lines and the second gate lines in the vertical direction,
the contact spacers further include second contact spacers along sidewalls of the third contacts.

10. The vertical memory device of claim 1 , further comprising:
a peripheral circuit on a peripheral portion of the substrate;
a mold protection layer covering top and lateral surfaces of the step portions, and the peripheral circuit; and
a peripheral circuit contact extending through the mold protection layer to the peripheral circuit, wherein
the peripheral circuit contact is electrically connected to the peripheral circuit, and
the peripheral circuit contact is in contact with the mold protection layer.

11. The vertical memory device of claim 1 , wherein the contacts are arranged in a zigzag arrangement along the parallel direction.

12. The vertical memory device of claim 1 , wherein the first gate lines are alternately stacked with the second gate lines such that the contact spacers are formed along the sidewalls of the first gate contacts on the step portions of either odd levels or even levels of the gate lines.

13. The vertical memory device of claim 1 , further comprising:
a peripheral circuit contact on a peripheral portion of the substrate, wherein
the contact spacers are not formed along a sidewall of the peripheral circuit contact.

14. A vertical memory device, comprising:
a substrate including a channel region, a contact region, and a peripheral circuit region;
a gate line structure on the substrate, the gate line structure including
gate lines on the channel region and the contact region, and stacked vertically from the substrate, the gate lines including step portions that extend to the contact region,
insulating interlayer patterns between the gate lines, and
channels extending vertically through the gate lines and the insulating interlayer patterns;

gate line contacts electrically connected to the gate lines on the contact region;
a peripheral circuit contact on the peripheral circuit region; and
contact spacers selectively formed along sidewalls of a portion of the gate line contacts, wherein
the contact spacers are not formed along a sidewall of the peripheral circuit contact.

15. The vertical memory device of claim 14 , wherein
the gate lines include first gate lines and second gate lines,
the first gate lines are either on top of the second gate lines or the first gate lines are alternately stacked with the second gate lines,
the insulating interlayer patterns are between the first gate lines and second gate lines,
the gate line contacts include first gate line contacts connected to the first gate lines and second gate line contacts connected to the second gate lines on the contact region, and
the contact spacers surround the first gate line contacts but not the second gate line contacts.

16. A vertical memory device, comprising:
a substrate;
vertical channel structures spaced apart from each other on the substrate,
gate lines surrounding the vertical channel structures,
the gate lines being spaced apart from each other in a vertical direction,
the gate lines including step portions that extend different extension lengths in a horizontal direction from a same one of the vertical channel structures,
the extension lengths of the step portions increasing from top to bottom,
the gate lines including first gate lines and second gate lines,
wherein the first gate lines are either on top of the second gate lines or the first gate lines are alternately stacked with the second gate lines;
contacts that extend vertically and connect to corresponding ones of the step portions, the contacts including first contacts connected to the first gate lines and second contacts connected to the second gate lines; and
contact spacers surrounding the first contacts, the contact spacers not surrounding the second contacts.

17. The vertical memory device of claim 16 , wherein
the first gate lines are on top of second gate lines,
the first contacts are connected to the step portions of the first gate lines, and
the second contacts are connected to the step portions of the second gate lines.

18. The vertical memory device of claim 16 , wherein the contact spacers include one of silicon nitride and

Assignees

• Lee Byung-Jin
• Kim Jee-Yong
• Byeon Dae-Seok
• Samsung Electronics Co Ltd

Inventors

• Lee Byung-Jin
• Kim Jee-Yong
• Byeon Dae-Seok

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11568

  Electricity · mapped topic

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/40

  characterised by the peripheral circuit region · CPC title