Methods for forming recesses in source/drain regions and devices formed thereof
US-12132089-B2 · Oct 29, 2024 · US
US8928149B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8928149-B2 |
| Application number | US-201313867905-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 22, 2013 |
| Priority date | Mar 12, 2013 |
| Publication date | Jan 6, 2015 |
| Grant date | Jan 6, 2015 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
A 3-D structure includes a stack of active layers at different depths has a plurality of contact landing areas on respective active layers within a contact area opening. A plurality of interlayer conductors, each includes a first portion within a contact area opening extending to a contact landing area, and a second portion in part outside the contact area opening above the top active layer. The first portion has a transverse dimension Y 1 that is nominally equal to the transverse dimension of the contact area opening, and the second portion having a transverse dimension Y 2 that is greater than the transverse dimension of the contact area opening. The active layers can be bit lines or word lines for a 3-D memory device, or other active layers in integrated circuits.
Opening claim text (preview).
What is claimed is: 1. A 3-D structure, comprising: a stack including a plurality of active layers at a corresponding plurality of depths in the stack, including a top active layer, and a plurality of contact landing areas on respective active layers; a first insulating layer over the top active layer, and having a contact area opening over the plurality of contact landing areas, the contact area opening having a longitudinal dimension and a transverse dimension; a second insulating layer over the first insulating layer, and filling the contact area opening and having a depth over the first insulating layer; a plurality of interlayer conductors in the second insulating layer, the interlayer connectors having a first portion within the contact area opening through the first insulating layer and extending to a corresponding one of said contact landing areas, and a second portion in part outside the contact area opening above the first insulating layer, said first portion having a transverse dimension Y 1 that is nominally equal to the transverse dimension of the contact area opening, and said second portion having a transverse dimension Y 2 that is greater than the transverse dimension of the contact area opening. 2. The 3-D structure of claim 1 , including a layer of material different than second insulating layer, between on sidewalls of the active layers in the plurality of contact landing areas. 3. The 3-D structure of claim 1 , wherein the contact landing areas have longitudinal pitches (e.g. sum of flat landing area and sidewall structure), and the contact area opening has a longitudinal dimension X L and a transverse dimension Y L , where X L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y L is less than X L ; and each interlayer conductor has a longitudinal dimension X V , where X V is less than the average longitudinal pitch of the contact landing areas, X V is less than Y 2 , and Y 2 is greater than Y L . 4. The 3-D structure of claim 1 , wherein the contact landing areas have longitudinal pitches (e.g. sum of flat landing area and sidewall structure), and the contact area opening has a longitudinal dimension X L and a transverse dimension Y L , where X L is equal to or greater than a sum of the longitudinal pitches of the contact landing areas, and Y L is less than X L . 5. The 3-D structure of claim 1 , wherein the first portion has a first longitudinal dimension X 1 and the second portion has a second longitudinal dimension X 2 , and the first longitudinal dimension X 1 and the second longitudinal dimension X 2 are nominally equal. 6. The 3-D structure of claim 1 , including a patterned conductor layer over the second portions of the plurality of interlayer conductors, and interlayer contacts between said second portions and the patterned conductor layer, at least some of said interlayer contacts being disposed over the contact area opening. 7. The 3-D structure of claim 1 , wherein said second portions of the plurality of interlayer conductors comprise patterned conductor lines having interlayer contacts to other elements outside of the contact area opening. 8. The 3-D structure of claim 1 , wherein said plurality of active layers comprise capacitor plates. 9. The 3-D structure of claim 1 , wherein said plurality of active layers comprise integrated circuits in a multichip package.
for dual-damascene structures · CPC title
in via holes or trenches · CPC title
of conductive parts of the interconnections · CPC title
using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title
Electricity · mapped topic
Related publications grouped by family.
Answers are generated from the same data shown on this page.