Three-dimensional three-port bit cell and method of assembling same

Patent metadata

Field	Value
Publication number	US-2016019946-A1
Application number	US-201414334935-A
Country	US
Kind code	A1
Filing date	Jul 18, 2014
Priority date	Dec 6, 2013
Publication date	Jan 21, 2016
Grant date	—

Abstract

A three-port, three-dimensional bit cell generally comprises a read portion of a cell disposed on a first tier. The read portion comprises a plurality of read port elements. The three-port bit cell further comprises a write portion of the cell disposed on a second tier that is vertically stacked with respect to the first tier. The first and second tiers are coupled using at least one via. The write portion comprises a plurality of write port elements.

First claim

What is claimed is:

1 . A three-dimensional, three-port bit cell comprising:
a write portion disposed on a first tier, wherein said write portion comprises a plurality of write port elements; and a read portion disposed on a second tier that is vertically stacked with respect to the first tier and coupled to the first tier using at least one via, wherein said read portion comprises a plurality of read port elements.

2 . The three-dimensional, three-port bit cell of claim 1 , wherein said write portion further comprises a plurality of write bit lines that each extends in a first direction in a first conductive layer of the first tier and said read portion further comprises a plurality of read bit lines that each extends in the first direction in a first conductive layer of the second tier.

3 . The three-dimensional, three-port bit cell of claim 2 , wherein said write portion further comprises at least one write word line that extends in a second direction that is different from the first direction in a second conductive layer of the first tier and said read portion further comprises at least one read word line that extends in the second direction in a second conductive layer of the second tier.

4 . The three-dimensional, three-port bit cell of claim 1 , wherein said plurality of read port elements comprises a plurality of read port gates.

5 . The three-dimensional, three-port bit cell of claim 4 , wherein said read portion further comprises at least one latch invertor disposed on the second tier and coupled to the plurality of read port gates.

6 . The three-dimensional, three-port bit cell of claim 4 , wherein said plurality of write port elements comprises a plurality of write port gates.

7 . The three-dimensional, three-port bit cell of claim 6 , wherein the three-port bit cell comprises a ten transistor cell, wherein said read port elements comprise a four transistor structure and said write port elements comprise a six transistor structure.

8 . The three-dimensional, three-port bit cell of claim 6 , wherein each of said plurality of read port gates and said plurality of write port gates is one of a NMOS device or a PMOS device.

9 . The three-dimensional, three-port bit cell of claim 1 , further comprising:
a write control circuit disposed on the first tier; and a read control circuit disposed on the second tier.

10 . The three-dimensional, three-port bit cell of claim 9 , wherein the read control circuit comprises a read port control circuit and a read word line decoder, and wherein the write control circuit comprises a write port control circuit and a write word line decoder.

11 . A semiconductor memory comprising:
a first tier comprising a first port array portion; a second tier vertically stacked with respect to said first tier using at least one via, wherein said second tier comprises a second port array portion; and at least one three-dimensional, three-port bit cell comprising:
a first portion disposed on said first port array portion, wherein said first portion comprises a plurality of write port elements; and
a second portion disposed on said second port array portion, wherein said second portion comprises a plurality of read port elements.

12 . The semiconductor memory of claim 11 , wherein said first portion further comprises a plurality of write bit lines that each extends in a first direction in a first conductive layer of said first tier and said second portion further comprises a plurality of read bit lines that each extends in the first direction in a first conductive layer of said second tier.

13 . The semiconductor memory of claim 12 , wherein said first portion further comprises at least one write word line that each extends in a second direction that is different from the first direction in a second conductive layer of said first tier and said second portion further comprises at least one read word line that each extends in the second direction in a second conductive layer of said second tier.

14 . The semiconductor memory of claim 11 , wherein said plurality of read port elements comprises a plurality of read port gates.

15 . The three-dimensional, three-port bit cell of claim 14 , wherein said second portion further comprises at least one latch invertor coupled to the plurality of read port gates.

16 . The semiconductor memory of claim 11 , further comprising a write port control circuit disposed on said first tier and a read port control circuit disposed on said second tier.

17 . The semiconductor memory of claim 11 , further comprising a write driver and a write word line decoder disposed on said first tier and a read input/output (I/O) circuit and a read word line decoder disposed on said second tier.

18 . A method comprising:
disposing a write portion of a three-dimensional, three-port bit cell onto a first tier, wherein the write portion includes a plurality of write port elements; disposing a read portion of the three-dimensional, three-port bit cell onto a second tier vertically stacked with respect to the first tier, wherein the read portion includes a plurality of read port elements; and coupling the first tier to the second tier using at least one via.

19 . The method of claim 18 , further comprising:
routing a first set of signals within the first tier for the plurality of write port elements; and routing a second set of signals within the second tier for the plurality of read port elements.

20 . The method of claim 18 , further comprising:
disposing at least one latch invertor on the second tier; and coupling the at least one latch invertor to the plurality of read port elements.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tzu-Kuei
• Liao Hung-Jen
• Chen Yen-Huei
• Wu Ching-Wei

Classifications

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/01

  Manufacture or treatment · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title