Semiconductor device package including bonding layer having Ag3Sn

Patent metadata

Field	Value
Publication number	US-9520377-B2
Application number	US-201414311708-A
Country	US
Kind code	B2
Filing date	Jun 23, 2014
Priority date	Oct 29, 2013
Publication date	Dec 13, 2016
Grant date	Dec 13, 2016

Abstract

Semiconductor device packages and methods of manufacturing the semiconductor device packages are provided. A semiconductor device package may include a bonding layer between a substrate and a semiconductor chip, and the bonding layer may include an intermetallic compound. The intermetallic compound may be a compound of metal and solder material. The intermetallic compound may include Ag 3 Sn. A method of manufacturing the semiconductor device package may include forming a bonding layer, which bonds a semiconductor chip to a substrate, by using a mixed paste including metal particles and a solder material. The bonding layer may be formed by forming an intermetallic compound, which is formed by heating the mixed paste to react the metal particles with the solder material.

First claim

What is claimed is:

1. A semiconductor device package comprising:
a first substrate;
at least one semiconductor chip mounted on the first substrate;
a first bonding layer provided between the first substrate and the semiconductor chip, the first bonding layer including Ag 3 Sn grains; and
a metal layer provided between the first bonding layer and the semiconductor chip, the metal layer including a non-solder material, the first bonding layer in contact with the metal layer and the first substrate,
wherein the first bonding layer is substantially devoid of pores,
wherein the Ag 3 Sn grains are substantially uniformly distributed throughout the first bonding layer, and the Ag 3 Sn grains are in contact with the first substrate, and
wherein the first bonding layer includes Ag material and the Ag 3 Sn gains, and the Ag material exists between the Ag 3 Sn grains.

2. The semiconductor device package of claim 1 , wherein a content of the Ag 3 Sn grains in the first bonding layer is equal to or greater than about 90 wt %.

3. The semiconductor device package of claim 1 , wherein the first bonding layer includes a mixture of the Ag material and the Ag 3 Sn grains.

4. The semiconductor device package of claim 1 , wherein the first bonding layer includes a mixture of the Ag material, the Ag 3 Sn grains, and a solder material.

5. The semiconductor device package of claim 4 , wherein a content of the solder material in the mixture is equal to or less than about 10 wt %.

6. The semiconductor device package of claim 1 , wherein a content of the Ag 3 Sn grains in the first bonding layer is equal to or greater than about 50 wt %.

7. The semiconductor device package of claim 1 , wherein the metal layer includes at least one of Al, Cu, Ni, Ag, Au, or an alloy thereof.

8. The semiconductor device package of claim 1 , wherein the first substrate is one selected from among a direct bonded copper (DBC) substrate, a direct bonded aluminum (DBA) substrate, a printed circuit board (PCB), and a lead frame.

9. The semiconductor device package of claim 1 , further comprising:
a plurality of semiconductor chips including the at least one semiconductor chip.

10. The semiconductor device package of claim 1 , further comprising:
a base plate attached to the first substrate; and
a second bonding layer provided between the base plate and the first substrate, the second bonding layer having a same configuration as the first bonding layer.

11. The semiconductor device package of claim 1 , wherein the first substrate is attached to a first surface of the semiconductor chip, and the semiconductor device package further comprises,
a second substrate attached to a second surface of the semiconductor chip, the second surface opposite to the first surface, and
a second bonding layer provided between the second substrate and the semiconductor chip, the second bonding layer having a same configuration as the first bonding layer.

12. The semiconductor device package of claim 11 , further comprising:
at least one of a first base plate attached to the first substrate and a second base plate attached to the second substrate.

13. The semiconductor device package of claim 1 , wherein the at least one semiconductor chip includes at least one power device.

14. The semiconductor device package of claim 1 , wherein the first bonding layer further includes a solder material, and
wherein a content of the solder material in the first bonding layer is equal to or less than 5 wt %.

15. The semiconductor device package of claim 1 , wherein the first bonding layer covers an entirety of a facing surface of the semiconductor chip.

16. The semiconductor device package of claim 1 , wherein a sum of contents of the Ag3Sn grains and the Ag material in the first bonding layer is equal to or greater than about 90 wt %.

17. The semiconductor device package of claim 1 , wherein a content of Ag in the first bonding layer is at least three times a content of Sn in the first bonding layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Jeong-Won
• Lee Baik-Woo
• Booh Seong-Woon
• Jeong Chang-Mo

Classifications

• B23K20/233

  without ferrous layer · CPC title

• B23K20/16

  with interposition of special material to facilitate connection of the parts, e.g. material for absorbing or producing gas · CPC title

• B23K35/0244

  Powders, particles or spheres; Preforms made therefrom · CPC title

• B23K20/023

  Thermo-compression bonding · CPC title

• B23K35/025

  Pastes, creams or slurries · CPC title