Coreless packaging substrate and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9510463-B2
Application number	US-201414583317-A
Country	US
Kind code	B2
Filing date	Dec 26, 2014
Priority date	Jul 17, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

First claim

What is claimed is:

1. A coreless packaging substrate, comprising:
a dielectric layer having opposite first and second surfaces;
a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads;
a plurality of protruding elements formed on the first conductive pads, respectively, and protruding from the first surface of the dielectric layer, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element;
a conductive layer formed on the contact surfaces of the protruding elements;
a second circuit layer formed on the second surface of the dielectric layer; and
a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer.

2. The coreless packaging substrate of claim 1 , wherein the contact surfaces of each of the protruding elements comprise upper and side surfaces of each of the protruding elements.

3. The coreless packaging substrate of claim 1 , wherein each of the protruding elements has a width less than or equal to that of the corresponding first conductive pad.

4. The coreless packaging substrate of claim 1 , wherein each of the protruding elements and the corresponding first conductive pad are made of a same material or integrally formed.

5. The coreless packaging substrate of claim 1 , wherein each of the protruding elements is a conductive post or a bonding pad, and the conductive element is a bump.

6. The coreless packaging substrate of claim 1 , wherein the second circuit layer has a plurality of second conductive pads and the conductive vias are formed between the first circuit layer and the second conductive pads.

7. The coreless packaging substrate of claim 1 , wherein the conductive layer is further formed on portions of the first conductive pads.

8. The coreless packaging substrate of claim 1 , further comprising another conductive layer formed between the protruding elements and the first conductive pads.

9. The coreless packaging substrate of claim 1 , further comprising an insulating layer formed on the second surface of the dielectric layer and the second circuit layer, wherein the insulating layer has a plurality of openings for exposing second conductive pads of the second circuit layer.

Assignees

• Siliconware Precision Industries Co Ltd

Inventors

• Pai Yu-Cheng
• Lin Chun-Hsien
• Chiu Shih-Chao
• Hsiao Wei-Chung
• Sun Ming-Chen
• Shen Tzu-Chieh
• Chen Chia-Cheng

Classifications

• H10P72/7424

  used as a support during the manufacture of self-supporting substrates · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title