Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-9508636-B2
Application number	US-201314368721-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Oct 16, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first lamination layer on a first side of a package substrate and a first surface finish on one or more electrical contacts disposed on a second side of the package substrate; removing the first lamination layer from the first side of the package substrate; depositing a second lamination layer on the second side of the package substrate and a second surface finish on the one or more electrical contacts disposed on the first side of the package substrate; and removing the second lamination layer from the second side of the package substrate. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A package substrate comprising:
a first side including one or more lands, the one or more lands having a first surface finish disposed on the one or more lands; and
a second side disposed opposite to the first side, the second side having die interconnect region, the die interconnect region having one or more electrical routing features embedded therein, the one or more electrical routing features having a second surface finish disposed on, and in direct contact with, the one or more electrical routing features, wherein the electrical routing features are configured to bond with die interconnect structures of one or more dies and the second surface finish has a different chemical composition than the first surface finish.

2. The package substrate of claim 1 , wherein the first surface finish is an outermost surface finish on the one or more lands and the second surface finish is an outermost surface finish on the one or more electrical routing features.

3. The package substrate of claim 1 , wherein the second surface finish is imidazole or an imidazole derivative.

4. The package substrate of claim 1 , wherein the second surface finish is gold.

5. The package substrate of claim 1 , wherein the second surface finish is a combination of palladium and gold.

6. The package substrate of claim 1 , wherein the second surface finish has a thickness of less than or equal to 500 nanometers.

7. The package substrate of claim 1 , wherein the first surface finish comprises nickel (Ni).

8. The package substrate of claim 7 , wherein the first surface finish further comprises one or both of palladium (Pd) or gold (Au).

9. The package substrate of claim 1 , wherein the die interconnect region is disposed in a dielectric layer.

10. The package substrate of claim 1 , wherein the die interconnect region comprises a silicon bridge.

11. The package substrate of claim 1 , wherein the one or more electrical routing features of the die interconnect region route electrical signals between a first die connected to the package substrate and a second die connected to the package substrate.

12. A package assembly comprising:
an integrated circuit (IC) chip having one or more input/output (I/O) connection points and one or more power connection points; and
a package substrate including:
a first side including one or more lands, the one or more lands having a first surface finish disposed on the one or more lands; and
a second side disposed opposite to the first side, the second side having a silicon connecting region embedded therein, the silicon connecting region having one or more electrical routing features embedded therein, the one or more electrical routing features having a second surface finish disposed on, and in direct contact with, the one or more electrical routing features, wherein the second surface finish has a different chemical composition than the first surface finish and the second surface finish is electrically connected to the one or more I/O connection points or the one or more power connection points.

13. The package assembly of claim 12 , wherein the IC chip is a processor.

14. The package assembly of claim 12 , further comprising one or more of an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, a Geiger counter, an accelerometer, a gyroscope, a speaker, or a camera coupled with the circuit board, wherein the package assembly is part of a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei
• Lotz Stefanie M

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/63

  Vias, e.g. via plugs · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title