Integrated vacuum microelectronic device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9508520-B2
Application number	US-201414290583-A
Country	US
Kind code	B2
Filing date	May 29, 2014
Priority date	May 31, 2013
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

An integrated vacuum microelectronic device comprises: a highly doped semiconductor substrate, at least one insulating layer) placed above said doped semiconductor substrate, a vacuum aperture formed within said at least one insulating layer and extending to the highly doped semiconductor substrate, a first metal layer acting as a cathode, a second metal layer placed under said highly doped semiconductor substrate and acting as an anode. The first metal layer is placed adjacent to the upper edge of the vacuum aperture and the vacuum aperture has a width dimension such as the first metal layer remains suspended over the vacuum aperture.

First claim

The invention claimed is:

1. An integrated vacuum microelectronic device comprising:
a doped semiconductor substrate,
at least one insulating layer placed above said doped semiconductor substrate,
a vacuum aperture formed within said at least one insulating layer and extending to the doped semiconductor substrate,
a first metal layer placed above said vacuum aperture and configured to act as a cathode, and
a second metal layer placed under said doped semiconductor substrate and configured to act as an anode,
wherein said first metal layer is placed adjacent to an upper edge of said vacuum aperture, said vacuum aperture having a width dimension such that the first metal layer remains suspended over and seals said vacuum aperture.

2. The integrated vacuum microelectronic device according to claim 1 , wherein said at least one insulating layer comprises two or more insulating layers of a stack that includes one or more conductive layers separating the two or more insulating layers from each other, said vacuum aperture is formed within said stack, the integrated vacuum microelectronic device comprising one or more electrodes contacting the one or more conductive layers of the stack.

3. The integrated vacuum microelectronic device according to claim 2 , comprising a further insulating layer placed on sidewalls of the vacuum aperture.

4. The integrated vacuum microelectronic device according to claim 3 , wherein said further insulating layer is made of silicon-nitride and has a thickness ranging from 50 to 100 nm.

5. The integrated vacuum microelectronic device according to claim 2 , wherein said one or more conductive layers are made of doped polysilicon, having a thickness between 300 nm and 500 nm and a resistivity ranging from 10 to 100 mΩ·cm.

6. The integrated vacuum microelectronic device according to claim 2 , wherein the at least one insulating layer includes three insulating layers, the device further comprising:
two conductive layers separating the three insulating layers from each other; the two conductive layers including a conductive grid layer; and
first and second metal paths electrically coupled to the conductive grid layer at two different contact points, the conductive grid layer being configured to act as a metal heater between the contact points.

7. The integrated vacuum microelectronic device according to claim 1 , wherein said vacuum aperture has a width dimension ranging from 350 nm to 550 nm.

8. The integrated vacuum microelectronic device according to claim 1 , wherein the vacuum aperture has a vacuum at a pressure of about 10 −5 Torr.

9. The integrated vacuum microelectronic device according to claim 1 , wherein said first metal layer has a thickness equal to at least a width dimension of the vacuum aperture.

10. A method for manufacturing an integrated vacuum microelectronic device, comprising:
forming a doped semiconductor substrate;
depositing at least one insulating layer over said doped semiconductor substrate,
forming a vacuum aperture within said at least one insulating layer, the vacuum aperture extending to the doped semiconductor substrate,
depositing a first metal layer over said vacuum aperture, said first metal layer being configured to act as a cathode,
forming a second metal layer under said doped semiconductor substrate, said second metal layer being configured to act as an anode,
wherein said first metal layer is placed adjacent to an upper edge of said vacuum aperture, said vacuum aperture having a width dimension such that the first metal layer remains suspended over and seals said vacuum aperture.

11. The method according to claim 10 , wherein depositing the at least one insulating layer includes forming two or more insulating layers of a stack and forming said vacuum aperture includes forming the vacuum aperture within said stack, the method comprising:
forming one or more conductive layers separating the two or more insulating layers from each other; and
forming one or more electrodes electrically contacting the conductive layers of the stack.

12. The method according to claim 11 , comprising, before depositing the first metal layer, depositing a further insulating layer over the stack, selectively removing said further insulating layer until said further insulating layer is only positioned on sidewalls of said vacuum aperture.

13. The method according to claim 12 , wherein said further insulating layer is made of silicon-nitride and has a thickness ranging from 50 nm to 100 nm.

14. The method according to claim 11 , wherein said one or more conductive layers are made of polysilicon, having a thickness comprised between 300 nm and 500 nm and a resistivity ranging from 10 to 100 mΩ·cm.

15. The method according to claim 10 , wherein said vacuum aperture has a width dimension ranging from 350 nm to 550 nm.

16. A method according to claim 10 , wherein the vacuum aperture has a vacuum at a pressure of about 10 −5 Torr.

17. A method according to claim 10 , wherein depositing the first metal layer occurs at a sufficiently low temperature that enables the first metal layer to be deposited faster in a horizontal direction than in other directions, and depositing the first metal layer forms protuberances extending from said upper edge towards the inside of the vacuum aperture, remaining suspended over said vacuum aperture, and uniting themselves.

18. The method according to claim 10 , wherein the said first metal layer has a thickness equal to at least a width dimension of the vacuum aperture.

19. An integrated vacuum microelectronic device comprising:
a doped semiconductor substrate,
a stack placed above said doped semiconductor substrate and including three insulating layers and two conductive layers separating the three insulating layers from each other; the two conductive layers including a conductive grid layer,
a vacuum aperture formed within said stack and within said insulating layers and extending to the doped semiconductor substrate,
a first metal layer placed above said vacuum aperture and configured to act as a cathode,
a second metal layer placed under said doped semiconductor substrate and configured to act as an anode,
one or more electrodes contacting the one or more conductive layers of the stack, and
first and second metal paths electrically coupled to the conductive grid layer at two different contact points, the conductive grid layer being configured to act as a metal heater between the contact points,
wherein said first metal layer is placed adjacent to an upper edge of said vacuum aperture, said vacuum aperture having a width dimension such that the first metal layer remains suspended over said vacuum aperture.

20. The integrated vacuum microelectronic device according to claim 19 , comprising a further insulating layer placed on sidewalls of the vacuum aperture.

21. The integrated vacuum microelectronic device according to claim 19 , wherein said first metal layer has a thickness equal to at least a width dimension of the vacuum aperture.

22. A method for manufacturing an integrated vacuum microelectronic device, comprising:
forming a doped semiconductor substrate;
depositing at least one insulating layer over said doped semiconductor substrate,
forming a vacuum aperture within said at least one insulating layer, the vacuum aperture extending to the doped semiconductor substrate,
depositing a first metal layer over said vacuum aperture, said first metal layer being configured to act as a ca

Assignees

• St Microelectronics Srl

Inventors

• Patti Davide Giuseppe

Classifications

• H01J21/105 Primary

  with microengineered cathode and control electrodes, e.g. Spindt-type · CPC title

• H01J9/027

  of thin film cathodes · CPC title

• H01J1/3044 Primary

  Point emitters · CPC title

• H01J9/025

  of field emission cathodes · CPC title