Elimination of defects in long aspect ratio trapping trench structures

Patent metadata

Field	Value
Publication number	US-9502245-B1
Application number	US-201615042211-A
Country	US
Kind code	B1
Filing date	Feb 12, 2016
Priority date	Dec 9, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method of forming a semiconductor in a long trench. The method may include; forming a first semiconductor on a substrate and in a long trench; forming a first spacer along sidewalls of the long trench and above the first semiconductor, a portion of the first semiconductor remains exposed; recessing the exposed portion of the first semiconductor; forming an insulator layer on the recessed portion of the first semiconductor; forming a second semiconductor on the insulator layer; forming a second spacer on sidewalls of the first spacer and above the second semiconductor, a portion of the second semiconductor remains exposed; removing the exposed portion of the second semiconductor; and removing a frond end and a back end of the first semiconductor and the second semiconductor, wherein the front end and back end are separated by a central region and the central region extends across the width of the long trench.

First claim

What is claimed is:

1. A method of removing defects in a semiconductor formed in a long aspect ratio trapping (ART) trench, the method comprising:
providing a dielectric layer on a substrate;
forming a long trench in the dielectric layer exposing the substrate, wherein a length of the long trench is longer than a width of the long trench;
forming a first semiconductor in the long trench;
recessing the first semiconductor to a first recessed depth below a top surface of the dielectric layer, and a top portion of a long trench sidewall is exposed;
forming a first spacer on the exposed top portion of the long trench sidewall, wherein a first spacer thickness is less than half of the width of the long trench, and a portion of the top surface of the first semiconductor is exposed;
recessing the exposed top surface of the first semiconductor to a second recessed depth below the top surface of the dielectric layer, wherein a sidewall portion of the first semiconductor remains on the long trench sidewalls directly below the first spacer, and the sidewall portion of the first semiconductor having growth defects;
forming an insulator layer on the recessed exposed top surface of the first semiconductor, wherein a portion of the sidewall portion of the first semiconductor remains exposed above the insulator layer;
forming a second semiconductor in the long trench, wherein defects in the sidewall portion of the first semiconductor extend through the second semiconductor and terminate at the insulator layer;
recessing the second semiconductor to a third recessed depth below the top surface of the dielectric layer, wherein the first spacer is exposed in the long trench above the second semiconductor;
forming a second spacer on the exposed first spacer in the long trench, wherein the thickness of the first and second spacers are less than half of the width of the long trench, and a portion of a top surface of the second semiconductor is exposed;
removing a portion of the second semiconductor between the exposed top surface of the second semiconductor and the insulator layer, wherein a sidewall portion of the second semiconductor remains on the sidewall portion of the first semiconductor, and the sidewall portion of the second semiconductor is directly below the second spacer;
removing the first spacer and the second spacer;
forming a mask above the first semiconductor and second semiconductor in a middle region of the long trench, wherein the middle region extends across the width of the semiconductor and is between a front end region and back end region of the long trench;
removing the first semiconductor and second semiconductor from above the insulator layer in the front end region and the back end region of the long trench; and
removing the mask.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• H10P14/29

  characterised by the substrates · CPC title

• H10P36/00

  Gettering within semiconductor bodies · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title