High aspect ratio trapping semiconductor with uniform height and isolated from bulk substrate

Patent metadata

Field	Value
Publication number	US-9293530-B1
Application number	US-201414541213-A
Country	US
Kind code	B1
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A method of forming an isolated device region. The isolated device region may include forming a first trench in a second dielectric and a first dielectric, the second dielectric is on the first dielectric, the first dielectric is on a substrate; growing a semiconductor channel in the first trench, a top portion of the semiconductor channel is a device region and a bottom portion of the semiconductor channel is a defect region; removing the second dielectric layer exposing a portion of device region; recessing the first dielectric layer exposing a trench region of the semiconductor channel, the trench region is a region between the device region and the defect region; removing the trench region of the semiconductor channel electrically isolating the device region from the defect region; and forming a barrier layer between the isolated device region and the defect region.

First claim

What is claimed is:

1. A method comprising:
forming a first trench through a second dielectric layer and a first dielectric layer, the first trench has a trench height extending from a top surface of the second dielectric layer to a top surface of the substrate, a portion of the first trench in the first dielectric layer has a first height equal to the thickness of the first dielectric layer, the first height is greater than half of a trench width, the second dielectric layer is on the first dielectric layer, and the first dielectric layer is on a substrate;
growing a semiconductor channel on the substrate using epitaxial growth within the first trench, the semiconductor channel extends up from the top surface of the substrate and the semiconductor channel has a height greater than a thickness of the first dielectric layer, the semiconductor channel has a first region below the second dielectric layer and a second region above the first dielectric layer, and the first region includes a defect region;
forming a cap on the semiconductor channel and within the first trench;
removing the second dielectric layer, sidewalls of the second region are exposed, and a portion of the top surface of the first dielectric layer is exposed;
forming a spacer on the exposed sidewalls of the second region extending from the cap to the top surface of the first dielectric layer;
recessing the first dielectric layer exposing a trench region of the semiconductor channel, the trench region is in the first region;
forming an undercut trench by removing the trench region using an isotropic etching technique; and
forming a barrier layer on the first dielectric layer and in the undercut trench, the barrier layer is an electrical isolation between the second region and the first region.

2. The method of claim 1 , further comprising:
recessing an exposed portion of the barrier layer a distance less than a thickness of the barrier layer; and
removing the spacer and the cap from the second region.

3. The method of claim 1 , wherein the substrate is a bulk silicon substrate.

4. The method of claim 1 , wherein the semiconductor channel is germanium.

5. The method of claim 1 , wherein the isotropic etching technique is a wet etch.

6. The method of claim 1 , wherein the barrier layer is a flowable oxide.

7. The method of claim 1 , wherein the second region is free of misfit dislocations.

8. A method comprising:
forming a first trench in a second dielectric layer and a first dielectric layer, the second dielectric layer is on the first dielectric layer, the first dielectric layer is on a substrate;
growing a semiconductor channel in the first trench, a top portion of the semiconductor channel is a device region and a bottom portion of the semiconductor channel is a defect region;
removing the second dielectric layer exposing a portion of device region;
recessing the first dielectric layer exposing a trench region of the semiconductor channel, the trench region is a region between the device region and the defect region;
removing the trench region of the semiconductor channel electrically isolating the device region from the defect region; and
forming a barrier layer between the isolated device region and the defect region.

9. The method of claim 8 , further comprising:
recessing an exposed portion of the barrier layer to a surface above the top surface of the recessed first dielectric layer.

10. The method of claim 8 , wherein the substrate is a bulk silicon substrate.

11. The method of claim 8 , wherein the semiconductor channel is germanium.

12. The method of claim 8 , wherein the trench region is removed using a wet etch.

13. The method of claim 8 , wherein the barrier layer is a flowable oxide.

14. The method of claim 8 , wherein the isolated device region is free of misfit dislocations.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P14/271

  characterised by the preparation of substrate for selective deposition · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10W10/011 Primary

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10D86/01

  Manufacture or treatment · CPC title