High speed and low power circuit structure for barrel shifter

Patent metadata

Field	Value
Publication number	US-9501260-B2
Application number	US-201314094794-A
Country	US
Kind code	B2
Filing date	Dec 3, 2013
Priority date	Jun 29, 2012
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. The encoding scheme using a sign magnitude to 2's complement converter allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

First claim

What is claimed is:

1. A method of shifting bits of an operand value comprising:
generating a first decoder signal and a second decoder signal using a sign magnitude to 2's complement converter circuit having a sign input which receives an input shift direction and having a magnitude input which receives an input shift amount;
deriving a first select signal from the first decoder signal using a first decoder circuit;
deriving a second select signal from the second decoder signal using a second decoder circuit;
selecting an intermediate shifted value from a first plurality of shifted values representing the operand value shifted by different integer multiples of a first shift level unit amount using a first selector controlled by the first select signal; and
selecting a raw shifted value from a second plurality of shifted values representing the intermediate shifted value shifted by different integer multiples of a second shift level unit amount using a second selector controlled by the second select signal, wherein
the operand value has 64 bits,
the first decoder signal has 3 bits,
the second decoder signal has 3 bits,
the first plurality of shifted values comprise eight shifted values each having 71 bits, and
the second plurality of shifted values comprise eight shifted values each having 64 bits.

2. The method of claim 1 wherein said generating includes computing an output result as a 2's complement of the input shift amount using the shift direction as a sign input, assigning a first portion of the output result to the first decoder signal, and assigning a second portion of the output result to the second decoder signal.

3. The method of claim 1 wherein the sign magnitude to 2's complement converter circuit generates the first and second decoder signals using no more than three stages of gates.

4. The method of claim 1 wherein the input shift direction has a logical high value to indicate a shift direction to the right, and has a logical low value to indicate a shift direction to the left.

5. The method of claim 1 further comprising converting the raw shifted data into final shifted data using an output multiplexer.

Assignees

• IBM

Inventors

• Yasuda Takeo

Classifications

• G06F5/015 Primary

  having at least two separately controlled shifting levels, e.g. using shifting matrices (G06F5/012 takes precedence) · CPC title

• G06F7/76

  Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data · CPC title