Variable-size flash translation layer

Patent metadata

Field	Value
Publication number	US-9495288-B2
Application number	US-201314055336-A
Country	US
Kind code	B2
Filing date	Oct 16, 2013
Priority date	Jan 22, 2013
Publication date	Nov 15, 2016
Grant date	Nov 15, 2016

Abstract

A method for using a variable-size flash translation layer is disclosed. Step (A) receives a read request to read data corresponding to a logical block address from a nonvolatile memory. Step (B) reads a particular entry of a map to obtain (i) a physical address of a particular page of the nonvolatile memory, (ii) an offset in the particular page to compressed data previously stored and (iii) a length of the compressed data. The particular entry is associated with the logical block address. Step (C) converts the offset and the length to (i) an address of a given read unit in the particular page and (ii) a number of the read units to be read. Step (D) reads from the particular page at most the number of the read units starting from the given read unit. An offset and length granularity are finer than one read unit.

First claim

The invention claimed is:

1. A method for using a variable-size flash translation layer, comprising the steps of:
receiving, at an apparatus from a host, a read request to read particular data corresponding to a logical block address from a nonvolatile memory of the apparatus;
reading a particular one of a plurality of entries in a map to obtain a physical address of a particular one of a plurality of pages of the nonvolatile memory, an offset in the particular page to compressed data previously stored in response to writing the compressed data corresponding to the logical block address, and a length of the compressed data, wherein the particular entry is associated with the logical block address;
converting the offset and the length to an address of a given one of a plurality of read units in the particular page, and a number of the read units to be read from the particular page; and
reading from the particular page at most the number of the read units starting from the given read unit, wherein a granularity of the offset and the length is finer than a size of one of the read units.

2. The method according to claim 1 , further comprising the steps of:
performing error correction decoding on each of the read units as read from the particular page to generate corrected data; and
extracting the compressed data from the corrected data according to both the offset in the particular page to the compressed data and the length of the compressed data.

3. The method according to claim 2 , further comprising the steps of:
decompressing the compressed data to generate return data; and
transferring the return data to the host.

4. The method according to claim 1 , wherein the number of the read units to be read is less than all of the read units in the particular page.

5. The method according to claim 1 , further comprising the step of:
determining that at least a portion of the compressed data is in one or more subsequent read units of a subsequent one of the pages of the nonvolatile memory based on both the offset in the particular page to the compressed data and the length of the compressed data combined with an amount of user data in the particular page.

6. The method according to claim 5 , further comprising the step of:
reading from the subsequent page at most the one or more subsequent read units.

7. The method according to claim 1 , wherein a first one of the pages of the nonvolatile memory includes a first number of the read units, a second one of the pages of the nonvolatile memory includes a second number of the read units, and the first number is different from the second number.

8. The method according to claim 1 , wherein a first one of the pages of the nonvolatile memory includes a first amount of user data, a second one of the pages of the nonvolatile memory includes a second amount of the user data, and the first amount is different from the second amount.

9. The method according to claim 1 , further comprising the steps of:
receiving a write request to write the particular data in the nonvolatile memory;
compressing the particular data to generate the compressed data that is smaller than the particular data;
writing in the particular page at least a portion of the compressed data; and
storing in the particular entry the physical address of the particular page, the offset in the particular page to the compressed data, and the length of the compressed data.

10. The method according to claim 9 , further comprising the step of:
writing in the particular page a header that includes at least a portion of the logical block address of the write request and the length.

11. The method according to claim 1 , wherein the logical block address is one of a plurality of logical block addresses and at least one of the read units of the number of the read units includes at least some different data corresponding to a different one of the logical block addresses.

12. The method according to claim 1 , wherein at least one of the read units of the number of the read units includes one or more headers and a portion of the compressed data.

13. An apparatus comprising:
a nonvolatile memory; and
a circuit configured to receive a read request from a host to read particular data corresponding to a logical block address from the nonvolatile memory, read a particular one of a plurality of entries in a map to obtain a physical address of a particular one of a plurality of pages of the nonvolatile memory, an offset in the particular page to compressed data previously stored in response to writing the compressed data corresponding to the logical block address and a length of the compressed data, wherein the particular entry is associated with the logical block address, convert the offset and the length to an address of a given one of a plurality of read units in the particular page and a number of the read units to be read from the particular page, and read from the particular page at most the number of the read units starting from the given read unit, wherein a granularity of the offset and the length is finer than a size of one of the read units.

14. The apparatus according to claim 13 , wherein the circuit is further configured to perform error correction decoding on each of the read units as read from the particular page to generate corrected data and extract the compressed data from the corrected data according to both the offset in the particular page to the compressed data and the length of the compressed data.

15. The apparatus according to claim 14 , wherein the circuit is further configured to decompress the compressed data to generate return data and transfer the return data to the host.

16. The apparatus according to claim 13 , wherein the number of the read units to be read is less than all of the read units in the particular page.

17. The apparatus according to claim 13 , wherein the circuit is further configured to determine that at least a portion of the compressed data is in one or more subsequent read units of a subsequent one of the pages of the nonvolatile memory based on both the offset in the particular page to the compressed data and the length of the compressed data combined with an amount of user data in the particular page.

18. The apparatus according to claim 17 , wherein the circuit is further configured to read from the subsequent page at most the one or more subsequent read units.

19. The apparatus according to claim 13 , wherein a first one of the pages of the nonvolatile memory includes a first number of the read units, a second one of the pages of the nonvolatile memory includes a second number of the read units, and the first number is different from the second number.

20. The apparatus according to claim 13 , wherein the apparatus is implemented as one or more integrated circuits.

Assignees

• Seagate Technology Llc

Inventors

• Cohen Earl T

Classifications

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F12/04

  Addressing variable-length words or parts of words · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G06F12/10

  Address translation · CPC title