Memory address translation

Patent metadata

Field	Value
Publication number	US-9274973-B2
Application number	US-201414269445-A
Country	US
Kind code	B2
Filing date	May 5, 2014
Priority date	Jan 6, 2011
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array including a first table having a first number of records, wherein each of the first number of records includes a second number of entries; and
a controller coupled to the array and including:
a second table having a first number of records, wherein each of the first number of records in the second table includes a second number of entries; and
a third table having a first number of records, wherein each of the first number of records in the third table includes a second number of entries, and wherein each of the second number of entries in each of the first number of records in the third table includes a physical address corresponding to a record in the second table.

2. The memory device of claim 1 , wherein each of the second number of entries in each of the first number of records in the first table includes a physical address corresponding to a data segment stored in the memory array.

3. The memory device of claim 1 , wherein each of the second number of entries in each of the first number of records in the first table includes a logical address.

4. The memory device of claim 1 , wherein each of the second number of entries in each of the first number of records in the second table includes a physical address corresponding to a record in the first table.

5. The memory device of claim 1 , wherein at least one of the first table and the second table have a variable size.

6. The memory device of claim 1 , wherein the controller includes a cache configured to store one or more of the first number of records of the first table.

7. A memory device, comprising:
a memory array including a first table having a first number of records; and
a controller coupled to the memory array and including:
a second table having a second number of records, wherein the second table includes:
a first sub-table having a first number of records, wherein each of the first number of records in the first sub-table includes a second number of entries; and
a second sub-table having a first number of records, wherein each of the first number of records in the second sub-table includes a second number of entries; and

a third table;

wherein at least one of the first table and the second table have a variable size.

8. The memory device of claim 7 , wherein the third table has a variable size.

9. The memory device of claim 7 , wherein the first table and the second table have a variable size.

10. A method of operating a memory device, comprising:
determining an entry in a record of a first table in a controller of the memory device;
determining, using the determined entry, an entry in a record of a second table in a memory array of the memory device;
determining an entry in a record of a third table in the controller of the memory device, wherein the determined entry in the record of the third table includes a physical address corresponding to the record of the first table; and
determining, using the determined entry in the record of the third table, the entry in the record of the first table.

11. The method of claim 10 , wherein the method includes changing a size of at least one of the first table and the second table.

12. The method of claim 10 , wherein the determined entry in the record of the third table corresponds to a logical address corresponding to a data segment stored in the memory array.

13. The method of claim 10 , wherein the method includes storing the record of the second table in the controller.

14. The method of claim 10 , wherein the method includes accessing a data segment stored in the memory array using the determined entry in the record of the second table.

Assignees

• Micron Technology Inc

Inventors

• Manning Troy A
• Culley Martin L
• Larsen Troy D

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/1004

  Compatibility, e.g. with legacy hardware · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• G06F12/0638

  Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70) · CPC title