Translation layer partitioned between host and controller

US9329991B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9329991-B2
Application numberUS-201314060799-A
CountryUS
Kind codeB2
Filing dateOct 23, 2013
Priority dateJan 22, 2013
Publication dateMay 3, 2016
Grant dateMay 3, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method for using a partitioned flash transition layer is disclosed. Step (A) receives, at an apparatus from a host, a write command having first write data. Step (B) generates second write data by compressing the first write data in the apparatus. The second write data generally has a variable size. Step (C) stores the second write data at a physical location in a nonvolatile memory. The physical location is a next unwritten location. Step (D) returns, from the apparatus to the host in response to the write command, an indication of the physical location.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of storing data utilizing a partitioned flash translation layer comprising the steps of: receiving, first data to be written from a host; and storing second data generated from the first data in a memory, wherein the first data is compressed to generate the second data, the second data has a size that is variable, the second data is stored among a plurality of physical locations in the memory, an initial physical location of the plurality of physical locations that hold the second data is a next unwritten location in the memory, the size of the second data is stored in a first partition of the flash translation layer local to the memory, and the initial physical location of the second data in the memory is stored in a second partition of the flash translation layer in the host. 2. The method according to claim 1 , further comprising the steps of: receiving a read command having the initial physical location of the second data from the host; reading the size of the second data from the first partition of the flash translation layer; and retrieving the second data by reading a portion of the memory based on the initial physical location and the size of the second data. 3. The method according to claim 2 , further comprising the steps of: recreating the first data by decompressing the second data as retrieved from the memory; and returning the first data as recreated to the host. 4. The method according to claim 1 , further comprising the step of: storing an identifier associated with the first data in the memory as at least a portion of a header associated with the second data. 5. The method according to claim 4 , further comprising the step of: maintaining a map in the host, wherein the map associates the identifier with the initial physical location of the second data in the memory. 6. The method according to claim 4 , wherein the identifier is a logical block address, the initial physical location is an address within one of a plurality of read units in the memory that hold the second data, and each of the plurality of read units comprises a respective portion of the second data and a respective error correction information that protects the respective portion of the second data. 7. The method according to claim 6 , wherein the memory has a plurality of pages, the address is in a first page of the plurality of pages that hold the second data, the first page includes a first number of the plurality of read units that hold the second data, a second page of the plurality of pages includes a second number of the plurality of read units that hold the second data, and the first number is different from the second number. 8. The method according to claim 1 , wherein the next unwritten location adjoins previously written data in a physical address space of the memory. 9. A method of storing data utilizing a partitioned flash translation layer, comprising the steps of: receiving the data to be written from a host, wherein the data has a size that is variable; and storing the data in a memory, wherein the data is stored among a plurality of physical locations in the memory, an initial physical location of the plurality of physical locations that hold the data is a next unwritten location in the memory, the size of the data is stored in a first partition of the flash translation layer local to the memory, and the initial physical location of the data in the memory is stored in a second partition of the flash translation layer in the host. 10. The method according to claim 9 , further comprising the steps of: receiving a read command having the initial physical location in the memory that holds the data from the host; reading the size of the data from the first partition of the flash translation layer; and retrieving the data by reading a portion of the memory based on the initial physical location and the size of the data. 11. The method according to claim 10 , further comprising the step of: returning the data to the host. 12. The method according to claim 9 , further comprising the step of: storing an identifier associated with the data in the memory as at least a portion of a header associated with the data. 13. The method according to claim 12 , further comprising the step of: maintaining a map in the host, wherein the map associates the identifier with the initial physical location of the data in the memory. 14. The method according to claim 12 , wherein the identifier is a logical block address, the initial physical location is an address within one of a plurality of read units in the memory that hold the data, and each of the plurality of read units comprises a respective portion of the data and a respective error correction information that protects the respective portion of the data. 15. The method according to claim 14 , wherein the memory has a plurality of pages, the address is in a first page of the plurality of pages that hold the data, the first page includes a first number of the plurality of read units that hold the data, a second page of the plurality of pages includes a second number of the plurality of read units that hold the data, and the first number is different from the second number. 16. The method according to claim 9 , wherein the next unwritten location adjoins previously written data in a physical address space of the memory. 17. An apparatus comprising: an interface configured to process a plurality of read/write operations to/from a memory; and a control circuit configured to receive first data from a host, and store second data generated from the first data in the memory, wherein the first data is compressed to generate the second data, the second data has a size that is variable, the second data is stored among a plurality of physical locations in the memory, an initial physical location of the plurality of physical locations that hold the second data is a next unwritten location in the memory, the size of the second data is stored in a first partition of a flash translation layer local to the memory, and the initial physical location of the second data in the memory is stored in a second partition of the flash translation layer in the host. 18. The apparatus according to claim 17 , wherein the interface and the control circuit are part of a solid-state drive controller. 19. The method according to claim 1 , wherein the steps are performed in a solid-state drive controller. 20. The method according to claim 9 , wherein the steps are performed in a solid-state drive controller.

Assignees

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Classifications

  • Logical to physical mapping or translation of blocks or pages · CPC title

  • using replacement algorithms · CPC title

  • Compressed data · CPC title

  • in block erasable memory, e.g. flash memory · CPC title

  • Management of blocks · CPC title

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What does patent US9329991B2 cover?
A method for using a partitioned flash transition layer is disclosed. Step (A) receives, at an apparatus from a host, a write command having first write data. Step (B) generates second write data by compressing the first write data in the apparatus. The second write data generally has a variable size. Step (C) stores the second write data at a physical location in a nonvolatile memory. The phys…
Who is the assignee on this patent?
Seagate Technology Llc
What technology area does this patent fall under?
Primary CPC classification G06F12/0246. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue May 03 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).