Delay lock loop

Patent metadata

Field	Value
Publication number	US-9490822-B1
Application number	US-201514967835-A
Country	US
Kind code	B1
Filing date	Dec 14, 2015
Priority date	Dec 2, 2015
Publication date	Nov 8, 2016
Grant date	Nov 8, 2016

Abstract

A delay lock loop including a selection unit, a delay unit, an elimination unit, and a phase detection unit is provided. The selection unit receives a non-inverted clock signal and an inverted clock signal and generates a first clock signal and a second clock signal according to an indication signal. The delay unit includes a delay factor and delays the first clock signal according to the delay factor to generate a third clock signal. The elimination unit is coupled to the selection unit and delays the second clock signal to generate a fourth clock signal. The phase detection unit is coupled to the delay unit and the elimination unit and generates the indication signal according to a phase difference between the third and fourth clock signals. The delay unit adjusts the delay factor according to the indication signal.

First claim

What is claimed is:

1. A delay lock loop, comprising:
a selection unit receiving a non-inverted clock signal and an inverted clock signal and generating a first clock signal and a second clock signal according to an indication signal;
a delay unit coupled to the selection unit, wherein the delay unit comprises a delay factor and delays the first clock signal according to the delay factor to generate a third clock signal;
an elimination unit coupled to the selection unit and delaying the second clock signal to generate a fourth clock signal; and
a phase detection unit coupled to the delay unit and the elimination unit and generating the indication signal according to a phase difference between the third and fourth clock signals,
wherein the delay unit adjusts the delay factor according to the indication signal.

2. The delay lock loop as claimed in claim 1 , further comprising:
a buffer unit coupled to the selection unit and processing an input clock signal to generate the non-inverted clock signal and the inverted clock signal;
a control unit coupled to the phase detection unit and the delay unit, wherein the control unit directs the delay unit to adjust the delay factor according to the indication signal; and
a lock unit coupled to the selection unit and the phase detection unit and generating a lock signal according to the indication signal,
wherein the selection unit receives the lock signal and outputting the first and second clock signals according to the lock signal.

3. The delay lock loop as claimed in claim 2 , wherein the selection unit uses one of the non-inverted clock signal and the inverted clock signal as the first clock signal and uses the other of the non-inverted clock signal and the inverted clock signal as the second clock signal.

4. The delay lock loop as claimed in claim 3 , wherein when a rising edge of the third clock signal leads a falling edge of the fourth clock signal, the indication signal is at a first level, the lock signal is maintained at the first level, and the selection signal uses the non-inverted clock signal as the first clock signal and uses the inverted clock signal as the second clock signal, and
wherein when the rising edge of the third clock signal is aligned with a rising edge of the fourth clock signal, the indication signal is changed from the first level to a second level, the lock signal is maintained at the second level, the lock signal does not changed when the indication signal is changed, and the selection signal uses the inverted clock signal as the first clock signal and uses the non-inverted clock signal as the second clock signal.

5. The delay lock loop as claimed in claim 4 , wherein when the rising edge of the third clock signal is aligned with the rising edge of the fourth clock signal, the control unit directs the delay unit to adjust the delay factor.

6. The delay lock loop as claimed in claim 1 , wherein when the delay factor is equal to an initial value, an initial time difference occurs between the non-inverted clock signal and the third clock signal, and wherein a time difference between the inverted clock signal and fourth clock signals is equal to the initial time difference.

7. The delay lock loop as claimed in claim 1 , wherein the delay unit comprises:
a first delay circuit delaying the first clock signal to generate a first output signal;
a second delay circuit delaying the first output signal to generate a second output
a first multiplexer receiving the first and second output signals and using the first or second output signal as the third clock signal according to the delay factor.

8. The delay lock loop as claimed in claim 7 , wherein the elimination unit comprises:
a third delay circuit delaying the third clock signal to generate the fourth clock signal;
a fourth delay circuit connected to the third delay circuit in series; and
a second multiplexer coupled to the third delay circuit,
wherein the structure of the third delay circuit is the same as the structure of the first delay circuit, the structure of the fourth delay circuit is the same as the structure of the second delay circuit, and the structure of the second multiplexer is the same as the structure of the first multiplexer.

9. The delay lock loop as claimed in claim 2 , wherein the buffer unit comprises:
a first buffer processing the input clock signal to generate the non-inverted clock signal; and
a first inverter inverting the input clock signal to generate the inverted clock signal.

Assignees

• Via Alliance Semiconductor Co Ltd

Inventors

• Si Qiang
• Jiang Fan

Classifications

• H03K5/134 Primary

  with field-effect transistors · CPC title

• H03K2005/00019

  Variable delay · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/0812

  and where no voltage or current controlled oscillator is used · CPC title