Method for fabricating three-dimensional semiconductor device using buried stop layer in substrate
US-2024268119-A1 · Aug 8, 2024 · US
Methods of forming under device interconnect structures
US9490201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9490201-B2 |
| Application number | US-201313798575-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 13, 2013 |
| Priority date | Mar 13, 2013 |
| Publication date | Nov 8, 2016 |
| Grant date | Nov 8, 2016 |
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Abstract
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Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of forming a structure comprising: forming at least one routing layer in a first substrate having a first bonding layer comprising a first semiconductor material wherein the first substrate does not include a device layer; forming a device layer in a second substrate having a second bonding layer comprising a second semiconductor material; and coupling the first substrate with the second substrate, wherein the first semiconductor material of the…
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Classifications
- H10P90/1914Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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- What does patent US9490201B2 cover?
- Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H10P90/1914. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Nov 08 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).