Emulation of LED input characteristics in BICMOS process

Patent metadata

Field	Value
Publication number	US-9484913-B2
Application number	US-201514642382-A
Country	US
Kind code	B2
Filing date	Mar 9, 2015
Priority date	Mar 11, 2014
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

An LED input emulator to interface a signal source designed for use with an LED optocoupler, to capacitive or other galvanic isolation circuitry, emulating LED forward and reverse bias voltages. VR reverse blocking circuitry includes MP 1 and MP 2 PMOS transistors coupled to an emulator anode port, and to emulate LED reverse bias voltage. VF control circuitry includes a variable resistance (MP 3 ) coupled between anode and cathode ports, and a current control circuit coupled to an output node, and to control current through the variable resistance to maintain a desired forward voltage at the output node. In an example embodiment, the VF control circuitry is implemented with an amplifier and a bandgap voltage reference circuit coupled to the output node, generating both reference and feedback voltages input to the amplifier to control the variable resistance.

First claim

The invention claimed is:

1. A system suitable to provide galvanic isolation between functional blocks, comprising:
a signal source block to drive source signals through an LED optocoupler characterized by a forward voltage and a reverse breakdown voltage;
an LED input emulator circuit with emulator anode and emulator cathode ports coupled to the signal source block, and an emulator output node, the LED input emulator circuit to emulate a forward voltage VF at the emulator output node, and a reverse bias voltage VR across the emulator anode and cathode ports; and
an isolation circuit, including a galvanic isolation interface that is not based on optocoupling, coupled to the emulator anode port, through the emulator output node, and to the emulator cathode port, to receive the source signals through the LED input emulator circuit;
the LED input emulator circuit including:
VR reverse blocking circuitry coupled between the emulator anode port and both the emulator output node and the emulator cathode port, to emulate the reverse bias voltage VR, including
MP 1 and MP 2 PMOS transistors drain-coupled to the emulator anode port, and gate-coupled to the emulator cathode port, with
MP 1 source-coupled to the emulator output node; and
MP 2 source-coupled to the emulator cathode port; and

VF control circuitry coupled to the emulator output node, to control the forward voltage VF at the emulator output node, including
a variable resistance circuit coupled between the emulator anode and cathode ports, to provide a variable resistance based on a VF control signal, and
a current control circuit coupled to the emulator output node, to generate the VF control signal to control current through the variable resistance circuit based on a voltage at the emulator output node to maintain the voltage at the emulator output node at the forward voltage VF.

2. The system of claim 1 , wherein the variable resistance circuit comprises:
an MP 3 PMOS transistor source coupled to the MP 2 PMOS transistor;
the MP 3 PMOS transistor gate-coupled to the VF control circuit, to receive the VF control signal and control the current through MP 3 .

3. The system of claim 1 , wherein the current control circuit comprises:
an amplifier including inverting and non-inverting inputs, and an amplifier output;
reference circuitry coupled to the non-inverting input, to provide a reference voltage corresponding to the forward voltage VF; and
feedback circuitry coupled between the emulator output node and the inverting input, to provide a feedback voltage corresponding to the voltage at the emulator output node;
the amplifier circuit to generate the VF control signal at the amplifier output based on the reference voltage and the feedback voltage.

4. The system of claim 3 , wherein the reference circuitry and the feedback circuit comprise bandgap circuitry, including:
Q 1 and Q 2 NPN transistors; and
a resistor network coupled to the Q 1 /Q 2 transistors;
the Q 1 /Q 2 transistors and the resistor network to generate VBE and ΔVBE voltages, such that
the amplifier generates the VF control voltage based on VBE and ΔVBE, thereby controlling the current through the variable resistance circuit,
the forward voltage VF corresponds to a bandgap reference voltage that is a function of VBE and ΔVBE.

5. The system of claim 1 , wherein the isolation circuit comprises a capacitor-based isolation circuit.

6. An LED input emulator circuit suitable to interface to a galvanic isolation block that is not based on optocoupling, comprising:
emulator anode and emulator cathode input ports, and an emulator output node, the LED input emulator circuit to emulate an LED forward voltage VF at the emulator output node, and an LED reverse bias voltage VR across the emulator anode and cathode ports;
VR reverse blocking circuitry coupled between the emulator anode input port and both the emulator output node and the emulator cathode input port, to emulate the LED reverse bias voltage VR, including
MP 1 and MP 2 PMOS transistors drain-coupled to the emulator anode input port, and gate-coupled to the emulator cathode input port, with
MP 1 source-coupled to the emulator output node; and
MP 2 source-coupled to the emulator cathode input port; and

VF control circuitry coupled to the emulator output node, to control the forward voltage VF at the emulator output node, including
a variable resistance circuit coupled between the emulator anode and cathode input ports, to provide a variable resistance based on a VF control signal, and
a current control circuit coupled to the emulator output node, to generate the VF control signal to control current through the variable resistance circuit based on a voltage at the emulator output node, to maintain the voltage at the emulator output node at the forward voltage VF.

7. The circuit of claim 6 , wherein the anode and cathode input ports are coupleable to a signal source block to drive source signals through an LED optocoupler characterized by a forward voltage VF and a reverse bias voltage VR.

8. The circuit of claim 6 , wherein the LED input emulator circuit is integrated with the galvanic isolation block.

9. The circuit of claim 6 , wherein the variable resistance circuit comprises:
an MP 3 PMOS transistor source coupled to the MP 2 PMOS transistor;
the MP 3 PMOS transistor gate-coupled to the VF control circuit, to receive the VF control signal and control the current through MP 3 .

10. The circuit of claim 6 , wherein the current control circuit comprises:
an amplifier including inverting and non-inverting inputs, and an amplifier output;
reference circuitry coupled to the non-inverting input, to provide a reference voltage corresponding to the forward voltage VF; and
feedback circuitry coupled between the emulator output node and the inverting input, to provide a feedback voltage corresponding to the voltage at the emulator output node;
the amplifier circuit to generate the VF control signal at the amplifier output based on the reference voltage and the feedback voltage.

11. The circuit of claim 10 , wherein the reference circuitry and the feedback circuit comprise bandgap circuitry, including:
Q 1 and Q 2 NPN transistors; and
a resistor network coupled to the Q 1 /Q 2 transistors;
the Q 1 /Q 2 transistors and the resistor network to generate VBE and ΔVBE voltages, such that
the amplifier generates the VF control voltage based on VBE and ΔVBE, thereby controlling the current through the variable resistance circuit,
the forward voltage VF corresponds to a bandgap reference voltage that is a function of VBE and ΔVBE.

12. The circuit of claim 6 , wherein the galvanic isolation block comprises a capacitor-based isolation circuit.

13. A method for interfacing a signal source block to drive source signals through an LED optocoupler characterized by a forward voltage and a reverse breakdown voltage, to a galvanic isolation block that is not based on optocoupling, the method comprising:
emulating a reverse bias voltage VR with reverse blocking circuitry coupled between an emulator anode port and both an emulator output node and an emulator cathode port, including
MP 1 and MP 2 PMOS transistors drain-coupled to the emulator anode port, and gate-coupled to the emulator cathode port, with
MP 1 source-coupled to the emulator output node; and
MP 2 source-coupled to the emulator cathode port; and

controlling a forward voltage VF at the emulator output node with VF control circuitry coupled to the emulator output node, including
a variable resistance circuit coupled between the emulator anode and cathode ports, f

Assignees

• Texas Instruments Inc

Inventors

• Baranwal Shailendra K
• Stout David W
• Premanath Abhijeeth A

Classifications

• H03K17/168

  in composite switches · CPC title

• H03K17/689 Primary

  with galvanic isolation between the control circuit and the output circuit (H03K17/78 takes precedence) · CPC title

• H04L25/0266

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title

• H03K17/567

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title