Level shifter

Patent metadata

Field	Value
Publication number	US-9484897-B2
Application number	US-201514661848-A
Country	US
Kind code	B2
Filing date	Mar 18, 2015
Priority date	Mar 18, 2015
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

Systems, methods, and apparatus for use in biasing and driving high voltage semiconductor devices using only low voltage transistors are described. The apparatus and method are adapted to control multiple high voltage semiconductor devices to enable high voltage power control, such as power amplifiers, power management and conversion and other applications wherein a first voltage is large compared to the maximum voltage handling of the low voltage control transistors. A DC/DC power conversion implementation from high input voltage to low output voltage using a novel level shifter which uses only low voltage transistors is also provided. Also presented is a level shifter in which floating nodes and high voltage capacitive coupling and control enable the high voltage control with low voltage transistors.

First claim

The invention claimed is:

1. A level shifter configured to control a high voltage device capable of withstanding a voltage higher than a first voltage, comprising:
a circuital arrangement comprising transistor devices, each transistor device configured to withstand a second voltage substantially lower than the first voltage;
a first supply terminal of the circuital arrangement, configured to carry a first switching voltage, the first switching voltage switching between a reference voltage and a voltage higher than the first voltage;
a second supply terminal of the circuital arrangement, configured to carry a second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and the second voltage;
an input terminal of the circuital arrangement, the input terminal configured to receive input timing control signals for controlling the high voltage device, the timing control signals configured to be coupled to the transistor devices of the circuital arrangement by way of a non-galvanic coupling; and
an output terminal of the circuital arrangement, the output terminal configured to provide an output timing control signal at a voltage higher than the first voltage to the high voltage device, the output timing control signal being based on the coupled input timing control signals.

2. The level shifter of claim 1 , wherein the non-galvanic coupling is one of: a) capacitive coupling, b) magnetic coupling, and c) optical coupling.

3. The level shifter of claim 1 , wherein the first voltage is equal to or higher than 10 volts, and the second voltage is equal to or lower than 5 volts.

4. The level shifter of claim 1 , wherein the first voltage is equal to or higher than 25 volts, and the second voltage is equal to or lower than 2.5 volts.

5. The level shifter of claim 1 , wherein the input timing control signals comprise a first timing control signal and a second timing control signal, the second timing control signal being an inverted version of the first timing control signal.

6. The level shifter of claim 5 , wherein the second timing control signal is further time shifted with respect to the first timing control signal.

7. The level shifter of claim 1 or claim 6 , wherein the non-galvanic coupling is a capacitive coupling.

8. The level shifter of claim 7 , wherein the capacitive coupling is configured to detect transitions of the first and the second timing control signals.

9. The level shifter of claim 8 , wherein the output timing control signal comprises a low state with a voltage level substantially equal to the first switching voltage and a high state with a voltage level substantially equal to the second switching voltage.

10. The level shifter of claim 9 , wherein a transition from the low state to the high state of the output timing control signal is based on concurrent detection of a pulse corresponding to a rising transition of the first timing control signal and a pulse corresponding to a falling transition of the second timing control signal.

11. The level shifter of claim 10 , wherein a transition from the high state to the low state of the output timing control signal is based on concurrent detection of a pulse corresponding to a falling transition of the first timing control signal and a pulse corresponding to a rising transition of the second timing control signal.

12. The level shifter of claim 8 , wherein the coupling comprises a first capacitive coupling in correspondence of the first timing control signal and a second capacitive coupling in correspondence of the second timing control signal.

13. The level shifter of claim 12 , wherein each of the first and the second capacitive couplings comprises two series connected capacitors and a common node between the series connected capacitors configured to receive the first and the second timing control signals respectively.

14. The level shifter of claim 13 , wherein a first capacitor of the two series connected capacitors is coupled via a resistor connected to a terminal of the first capacitor away from the common node to the first supply terminal, and a second capacitor of the two series connected capacitors is coupled via a resistor connected to a terminal of the second capacitor away from the common node to the second supply terminal.

15. The level shifter of claim 14 , wherein a plurality of transistor devices of the transistor devices of the circuital arrangement are configured as discharge transistors to shorten pulse signals in correspondence of detected transitions at the terminals of the first capacitor and the second capacitor away from the common node.

16. The level shifter of claim 15 , wherein the discharge transistors are connected in parallel to the resistor connected to the first capacitor and to the resistor connected to the second capacitor, and are configured to discharge the first and the second capacitors.

17. The level shifter of claim 14 , wherein a transistor of the transistor devices of the circuital arrangement is configured to operate as an inverter to invert positive pulse signals in correspondence of detected rising transitions at the terminal of the first capacitor away from the common node.

18. The level shifter of claim 14 , wherein a plurality of transistors devices of the transistor devices of the circuital arrangement are configured as clamp circuits to limit an instantaneous voltage of pulse signals in correspondence of the detected transitions between the first switching supply and the second switching supply.

19. The level shifter of claim 18 , wherein the clamp circuits are further configured to remove negative pulse signals in correspondence of detected falling transitions of the first and the second timing control signals at the terminal of the first capacitor away from the common node, and to remove positive pulse signals in correspondence of detected rising transitions of the first and the second timing control signals at the terminal of the second capacitor away from the common node.

20. The level shifter of claim 1 , wherein the transistor devices of the circuital arrangement comprise one of: a) a silicon on sapphire (SOS) transistor structure, b) a silicon on insulator (SOI) transistor structure, and c) a bulk silicon (Si) transistor structure.

21. The level shifter of claim 20 , wherein a) comprises a reference terminal connected to a sapphire substrate of the transistor structure, the reference terminal is coupled to a DC voltage, and a thickness of the sapphire substrate is selected such as to withstand a voltage drop equal to or larger than the first switching voltage.

22. The level shifter of claim 21 , wherein the DC voltage is the reference voltage.

23. The level shifter of claim 21 , wherein a thickness of the sapphire structure is in a range of 10's to 100's micrometers.

24. The level shifter of claim 20 , wherein b) comprises a reference terminal connected to a silicon layer of the transistor structure, the reference terminal being coupled to a DC voltage.

25. The level shifter of claim 24 , wherein the DC voltage is the reference voltage.

26. The level shifter of claim 24 , wherein b) further comprises a buried silicon dioxide layer whose silicon dioxide thickness is capable of withstanding a voltage drop equal to or larger than the first switching voltage.

27. The level shi

Assignees

• Peregrine Semiconductor Corp

Inventors

• Green Merlin
• Burgener Mark L
• Swonger James W
• Abesingha Buddhika
• Reedy Ronald Eugene

Classifications

• H03K3/356104 Primary

  using complementary field-effect transistors (H03K3/35625 takes precedence) · CPC title

• H03K19/018514 Primary

  with at least one differential stage (H03K19/018528 and H03K19/018542 take precedence) · CPC title

• H03K17/689 Primary

  with galvanic isolation between the control circuit and the output circuit (H03K17/78 takes precedence) · CPC title

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title