Adjustable losses of bond wire arrangement

Patent metadata

Field	Value
Publication number	US-2016269022-A1
Application number	US-201315033869-A
Country	US
Kind code	A1
Filing date	Nov 7, 2013
Priority date	Nov 7, 2013
Publication date	Sep 15, 2016
Grant date	—

Abstract

The invention provides a bond wire arrangement comprising a signal bond wire ( 1 ) for operably connecting a first electronic device ( 6 ) to a second electronic device ( 8 ), and a control bond wire ( 2 ) being arranged alongside the signal bond wire at a distance so as to have a magnetic coupling with the signal bond wire ( 1 ), and having a first end ( 11 ) coupled to ground, and a second end ( 12 ) coupled to ground via a resistive element ( 14 ). The proposed solution allows the control of the Q factor (losses) of wire bond inductors during assembly phase, which will save time and reduce overall design cycle as compared to known methods.

First claim

1 . A bond wire arrangement comprising:
a signal bond wire for operably connecting a first device to a second device; and a first control bond wire being arranged alongside said signal bond wire at a distance so as to have a magnetic coupling with said signal bond wire, and having a first end coupled to ground, and a second end coupled to ground via a resistive element.

2 . A bond wire arrangement according to claim 1 , said resistive element having a resistance between 0.2 Ohm and- 5 Ohm.

3 . A bond wire arrangement according to claim 1 , wherein the resistive element comprises a resistor.

4 . A bond wire arrangement according to claim 1 , wherein the resistive element comprises a semiconductor layer.

5 . A bond wire arrangement according to claim 1 , wherein a coupling factor between said signal bond wire and said first control bond wire is between 0.1-0.7.

6 . A bond wire arrangement according to claim 1 , wherein the distance between said signal bond wire and said first control bond wire is between less than 200 microns.

7 . A bond wire arrangement according to claim 1 , wherein said bond wire arrangement comprises a capacitor arranged in series with said resistive element.

8 . A bond wire arrangement according to claim 1 , wherein a second control bond wire is arranged alongside said signal bond wire at a second distance so as to have a magnetic coupling with said signal bond wire, said second control bond wire being arranged at a side of the signal bond wire opposite from a side where said first control bond wire is arranged.

9 . A bond wire arrangement according to claim 1 , wherein the bond wire arrangement comprises an array of signal bond wires.

10 . A bond wire arrangement according to claim 1 , wherein the bond wire arrangement comprises an array of control bond wires.

11 . A power amplifier circuit comprising:
a radio frequency (RF) match network that includes a bypass network with a bond wire arrangement, wherein the bond wire arrangement includes a signal bond wire for operably connecting a first device to a second electronic device, and a control bond wire being arranged alongside said signal bond wire at a distance so as to have a magnetic coupling with said signal bond wire, and having a first end coupled to ground, and a second end coupled to ground via a resistive element.

12 . A power amplifier circuit according to claim 11 , wherein the bypass network comprises a bypass inductor arranged in series with a decoupling capacitor, said bypass inductor being embodied by the signal bond wire of the bond wire arrangement.

13 . A power amplifier circuit according to claim 11 , wherein the RF match network comprises a shunt inductor and a DC blocking capacitor arranged in series with said shunt inductor so as to connection an output lead of the power amplifier circuit and ground.

14 . (canceled)

15 . A RF circuit comprising:
a wire bond arrangement that includes
a signal bond wire for operably connecting a first device to a second device, and
a control bond wire being arranged alongside said signal bond wire at a distance so as to have a magnetic coupling with said signal bond wire, and having a first end coupled to ground, and a second end coupled to ground via a resistive element.

16 . A RF circuit according to claim 15 , wherein said wire bond arrangement is arranged in a final stage of said RF.

17 . (canceled)

18 . A RF integrated circuit according to claim 16 , wherein said final stage comprises:
an input terminal; a switching device having a control terminal, a first output terminal and a second output terminal, said control terminal being coupled to said input terminal; a first inductance embodied by said signal bond wire, having a first and second connector, said first connector being coupled to said input terminal; and a first capacitance having a first and second connector, said first connector of said first capacitance being coupled to said second connector of said first inductance, and said second connector of said first capacitance being coupled to ground.

19 . A RF circuit according to claim 15 , wherein said wire bond arrangement is arranged in a driver stage of said RF circuit.

20 . A RF circuit according to claim 19 , wherein said driver stage comprises:
an input terminal; a switching device having a control terminal, a first output terminal and a second output terminal, said control terminal being coupled to said input terminal; a first inductance embodied by said signal bond wire, having a first and second connector, said first connector being coupled to said input terminal; and a first capacitance having a first and second connector, said first connector of said first capacitance being coupled to said second connector of said first inductance, and said second connector of said first capacitance being coupled to ground.

Assignees

• Freescale Semiconductor Inc

Inventors

• Volokhine Youri

Classifications

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W80/754

  having material changed during the connecting · CPC title

• H10W72/07553

  changes in shapes · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title