Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET

US9105745B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9105745-B2
Application numberUS-201213630235-A
CountryUS
Kind codeB2
Filing dateSep 28, 2012
Priority dateJun 18, 2009
Publication dateAug 11, 2015
Grant dateAug 11, 2015

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T inv and V t of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the V t of the pFET becoming closer to the V t of a similarly constructed nFET with scaled T inv values.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a semiconductor structure comprising: providing a semiconductor substrate comprising a semiconductor material; forming a p-type field effect transistor (pFET) disposed upon said semiconductor substrate and comprising a semiconductor channel region comprised of SiGe formed upon or within a surface of said semiconductor substrate; forming a gate dielectric comprising an oxide layer overlying said semiconductor channel region comprised o…

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Next steps

Free tools are coming soon. Tell us what you want to track and we'll notify you.

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9105745B2 cover?
A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer…
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10D84/0167. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 11 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).