Metal gates for semiconductor devices and method thereof
US-2024429281-A1 · Dec 26, 2024 · US
US9105745B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9105745-B2 |
| Application number | US-201213630235-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 28, 2012 |
| Priority date | Jun 18, 2009 |
| Publication date | Aug 11, 2015 |
| Grant date | Aug 11, 2015 |
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A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in T inv and V t of the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the V t of the pFET becoming closer to the V t of a similarly constructed nFET with scaled T inv values.
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What is claimed is: 1. A method of forming a semiconductor structure comprising: providing a semiconductor substrate comprising a semiconductor material; forming a p-type field effect transistor (pFET) disposed upon said semiconductor substrate and comprising a semiconductor channel region comprised of SiGe formed upon or within a surface of said semiconductor substrate; forming a gate dielectric comprising an oxide layer overlying said semiconductor channel region comprised o…
Electricity · mapped topic
Electricity · mapped topic
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