Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Patent metadata

Field	Value
Publication number	US-9219154-B1
Application number	US-201414331857-A
Country	US
Kind code	B1
Filing date	Jul 15, 2014
Priority date	Jul 15, 2014
Publication date	Dec 22, 2015
Grant date	Dec 22, 2015

Abstract

Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.

First claim

What is claimed is:

1. A method of forming a semiconductor structure comprising:
providing a semiconductor-containing fin structure on a surface of a base layer, wherein said semiconductor-containing fin structure comprises, from bottom to top, and in an alternating manner, at least one first semiconductor material portion having a first oxidation rate, and at least one second semiconductor material portion having a second oxidation rate, wherein said first oxidation rate is slower than the second oxidation rate;
performing an oxidation process to form a continuous oxide liner on semiconductor sidewall surfaces of said semiconductor-containing fin structure, wherein said continuous oxide liner comprises a first oxide liner portion having a first thickness and located on each of said first semiconductor material portions and a second oxide liner portion having a second thickness that is greater than the first thickness and located on each of said second semiconductor material portions;
completely removing said first oxide liner portion from each of said first semiconductor material portions, while partially removing said second oxide liner portion from each of said second semiconductor material portions; and
epitaxially growing a semiconductor material protruding portion from an exposed semiconductor sidewall surface of each of said first semiconductor material portions.

2. The method of claim 1 , further comprising forming a gate structure surrounding said semiconductor-containing fin structure, wherein said gate structure comprises a gate dielectric material portion and a gate electrode material portion.

3. The method of claim 1 , wherein said oxidation process provides remaining first semiconductor material portions having a first thickness and remaining second semiconductor material portions having a second thickness that are less than the first thickness.

4. The method of claim 2 , wherein each of said second oxide liner portions has sidewalls that extend beyond sidewalls of each of said first oxide liner portions.

5. The method of claim 1 , wherein each of said semiconductor material protruding portions has a shape of a triangular and wherein a base of said triangular is formed directly on said exposed semiconductor sidewall surface of each of said least one first semiconductor material portions.

6. The method of claim 1 , wherein said providing the semiconductor-containing fin structure comprises:
providing a semiconductor-containing layer of a first semiconductor material on said surface of said base layer;
forming an initial second semiconductor material on said semiconductor-containing layer, wherein said first semiconductor material has said slower oxidation rate than said second semiconductor material;
forming a hard mask material atop said initial second semiconductor layer; and
patterning.

7. The method of claim 6 , further comprising forming alternating layers of said first semiconductor material and said second semiconductor material on said initial second semiconductor material.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Doris Bruce B
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P14/6306

  of the semiconductor materials · CPC title