Fin-FET with mechanical stress of the fin perpendicular to the substrate direction

US9024364B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9024364-B2
Application numberUS-201213599613-A
CountryUS
Kind codeB2
Filing dateAug 30, 2012
Priority dateMar 12, 2012
Publication dateMay 5, 2015
Grant dateMay 5, 2015

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial stripe shaped layers disposed horizontally on the side surface of the fin at different heights, and an interlayer dielectric disposed on the semiconductor substrate to cover the fin and applying a stress to the fin and the epitaxial layers. Any two adjacent epitaxial layers along the fin height direction determine a gap and the gaps between adjacent layers increase or decrease with increasing distance from the substrate.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a semiconductor substrate; a fin disposed on a surface of the semiconductor substrate; an insulator including a gate insulator, said gate insulator disposed on side surfaces of the fin; a gate electrode disposed on the insulator that is disposed on the side surfaces of the fin and also disposed on an upper surface of the fin; a plurality of epitaxial stripe shaped layers disposed horizontally on the side surfa…

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What does patent US9024364B2 cover?
A semiconductor device in one embodiment includes a semiconductor substrate, a fin disposed on a surface of the semiconductor substrate, an insulator including a gate insulator disposed on a side surface of the fin, and a gate electrode disposed on the insulator that is disposed on side surfaces of the fin and an upper surface of the fin. The device further includes a plurality of epitaxial str…
Who is the assignee on this patent?
Okano Kimitoshi, Toshiba Kk
What technology area does this patent fall under?
Primary CPC classification H10D30/62. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 05 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).