Gate and source/drain contact structures for a semiconductor device

Patent metadata

Field	Value
Publication number	US-9478662-B2
Application number	US-201615063604-A
Country	US
Kind code	B2
Filing date	Mar 8, 2016
Priority date	Mar 9, 2015
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

One illustrative device disclosed herein includes, among other things, a dielectric layer disposed above a source/drain region and a gate structure of a transistor, a first conductive contact positioned in the dielectric layer and contacting the gate structure, wherein a first spacer is disposed on a sidewall of the first conductive contact, and a second conductive contact positioned in the dielectric layer and contacting the source/drain region, wherein the first spacer at least partially defines a spacing between the first conductive contact and the second conductive contact.

First claim

What is claimed:

1. A semiconductor device, comprising:
a substrate;
a source/drain region defined in said substrate;
a conductive gate structure;
a dielectric layer disposed above said source/drain region and said conductive gate structure;
a first conductive contact positioned in said dielectric layer that conductively contacts said conductive gate structure, wherein a first dielectric spacer is disposed on all sidewalls of said first conductive contact; and
a second conductive contact positioned in said dielectric layer that conductively contacts said source/drain region, wherein said first dielectric spacer at least partially defines a spacing between said first conductive contact and said second conductive contact.

2. The device of claim 1 , further comprising a second dielectric spacer defined on a sidewall of said second conductive contact, wherein said first dielectric spacer and said second dielectric spacer define said spacing between said first conductive contact and said second conductive contact.

3. The device of claim 1 , wherein said gate structure comprises a metal gate electrode.

4. The device of claim 1 , further comprising epitaxial material disposed on a top portion of said source/drain region, wherein said second conductive contact contacts said epitaxial material.

5. The device of claim 1 , wherein said first dielectric spacer is positioned on all sidewalls of said first conductive contact and said first dielectric spacer surrounds said first conductive contact.

6. The device of claim 2 , wherein said first dielectric spacer is positioned on all sidewalls of said first conductive contact and said first dielectric spacer surrounds said first conductive contact and wherein said second dielectric spacer is positioned on all sidewalls of said second conductive contact and said second dielectric spacer surrounds said second conductive contact.

7. The device of claim 6 , wherein a portion of said first dielectric spacer contacts a portion of said second dielectric spacer.

8. The device of claim 1 , wherein said first dielectric spacer contacts both said first conductive contact and said second conductive contact.

9. The device of claim 1 , wherein said first dielectric spacer contacts said first conductive contact and said second dielectric spacer but does not contact said second conductive contact, and said second dielectric spacer contacts said second conductive contact and said first dielectric spacer but does not contact said first conductive contact.

10. The device of claim 1 , wherein said first dielectric spacer comprises a material that is different from and may be selectively etched relative to said dielectric layer.

11. The device of claim 1 , wherein said first conductive contact comprises a first long axis and said second conductive contact comprises a second long axis and wherein said first long axis and said second long axis are oriented orthogonally to one another.

12. A semiconductor device, comprising:
a substrate;
a source/drain region defined in said substrate;
a conductive gate structure;
a dielectric layer disposed above said source/drain region and said conductive gate structure;
a first conductive contact positioned in said dielectric layer that conductively contacts said conductive gate structure;
a first dielectric spacer positioned on all sidewalls of said first conductive contact; and
a second conductive contact positioned in said dielectric layer that conductively contacts said source/drain region, wherein said first dielectric spacer physically contacts both said first conductive contact and said second conductive contact.

13. The device of claim 12 , further comprising epitaxial material disposed on a top portion of said source/drain region, wherein said second conductive contact conductively contacts said epitaxial material.

14. The device of claim 12 , wherein said first dielectric spacer surrounds said first conductive contact.

15. The device of claim 12 , wherein said first conductive contact comprises a first long axis and said second conductive contact comprises a second long axis and wherein said first long axis and said second long axis are oriented orthogonally to one another.

16. A semiconductor device, comprising:
a substrate;
a source/drain region defined in said substrate;
a conductive gate structure;
a dielectric layer disposed above said source/drain region and said conductive gate structure;
a first conductive contact positioned in said dielectric layer that conductively contacts said conductive gate structure;
a first dielectric spacer that is disposed on all sidewalls of said first conductive contact;
a second conductive contact positioned in said dielectric layer that conductively contacts said source/drain region; and
a second dielectric spacer that is disposed on all sidewalls of said second conductive contact, wherein said first dielectric spacer and said second dielectric spacer, collectively, at least partially define a spacing between said first conductive contact and said second conductive contact.

17. The device of claim 16 , wherein said first dielectric spacer surrounds said first conductive contact and said second dielectric spacer surrounds said second conductive contact.

18. The device of claim 16 , wherein said first dielectric spacer contacts said first conductive contact and said second dielectric spacer but does not contact said second conductive contact, and said second dielectric spacer contacts said second conductive contact and said first dielectric spacer but does not contact said first conductive contact.

19. The device of claim 16 , wherein said first conductive contact comprises a first long axis and said second conductive contact comprises a second long axis and wherein said first long axis and said second long axis are oriented orthogonally to one another.

Assignees

• Globalfoundries Inc

Inventors

• Labonte Andre
• Xie Ruilong

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/076 Primary

  in via holes or trenches · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D64/62

  Electrodes ohmically coupled to a semiconductor · CPC title