Reduced resistance finFET device with late spacer self aligned contact

Patent metadata

Field	Value
Publication number	US-9112031-B2
Application number	US-201314075033-A
Country	US
Kind code	B2
Filing date	Nov 8, 2013
Priority date	Nov 8, 2013
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

Embodiments include a method of fabricating a reduced resistance finFET device comprising providing a fin in a semiconductor substrate. A dummy gate is formed over a portion of the fin such that the dummy gate does not initiate selective epitaxy. A source/drain region is formed on the fin such that the source/drain region directly contacts the dummy gate. The dummy gate is replaced with a replacement metal gate structure that directly contacts the source/drain region. A portion of the fin that includes a portion of the source/drain region is replaced with a contact material.

First claim

What is claimed is:

1. A finFET device, the device comprising:
a fin formed in a semiconductor substrate;
a source/drain region formed over a portion of the fin;
a gate structure formed over at least a portion of the fin, wherein the gate structure directly contacts a portion of the formed source/drain region;
an insulating layer over at least a portion of the fin, the source/drain region and the gate structure;
a spacer formed on at least a sidewall of the gate structure…

Assignees

• IBM

Inventors

• Leobandung Effendi

Classifications

• H10D30/024

  Electricity · mapped topic

• H10D30/62 Primary

  Electricity · mapped topic

• H10D64/017

  Electricity · mapped topic

• H10D30/0243

  Electricity · mapped topic

• H01L29/6681

  Electricity · mapped topic