Methods of generating integrated circuit layout using standard cell library

Patent metadata

Field	Value
Publication number	US-9460259-B2
Application number	US-201514832325-A
Country	US
Kind code	B2
Filing date	Aug 21, 2015
Priority date	Aug 22, 2014
Publication date	Oct 4, 2016
Grant date	Oct 4, 2016

Abstract

Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

First claim

What is claimed is:

1. A computer-implemented method of fabricating an integrated circuit (IC), comprising:
executing on a processor;
forming at least one standard cell, the forming at least one standard cell including,
providing a first active area disposed adjacent to a first cell boundary line, and the first active area being spaced apart from the first cell boundary line by a first distance,
providing a second active area disposed adjacent to a second cell boundary line, the second cell boundary line opposing the first cell boundary line, and the second active area being spaced apart from the second cell boundary line by a second distance, and
forming fins on the first and second active areas, the fins extending in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction,
the forming fins including,
forming at least first active fin on the first active area,
forming at least one first dummy fin between the first cell boundary line and the first active area, a boundary line of the first active area being between the at least one first dummy fin and the at least one first active fin,
forming at least one second active fin on the second active area, and
forming at least one second dummy fin between the second cell boundary line and the second active area, a boundary line of the second active area being between the at least one second dummy fin and the at least one second active fin,
the first cell boundary line being parallel to the fins, and
the first distance and the second distance remaining constant when a number of the fins on the first and second active areas is changed;

generating a layout using the at least one standard cell; and
fabricating the IC from the generated layout.

2. The method of claim 1 , further comprising:
decreasing a space between the first active area and the second active area when lengths of the first and second active areas in the second direction are increased.

3. The method of claim 1 , further comprising:
adjusting lengths of the first and second active areas in the second direction while the first and second distances remain constant.

4. The method of claim 1 , wherein the first distance is substantially equal to the second distance.

5. The method of claim 1 , wherein the forming fins further includes
forming the at least one first and second dummy fins respectively on first and second dummy areas, the first and second active areas not being disposed in the first and second dummy areas.

6. The method of claim 1 , wherein the forming fins further includes
forming at least one third dummy fin between the first active area and second active area.

7. The method of claim 1 , wherein a number of the at least one first dummy fin is equal to a number of the at least one second dummy fin.

8. The method of claim 6 , further comprising:
reducing a number of the at least one third dummy fin when a number of the active fins is increased.

9. The method of claim 1 , further comprising:
adjusting a number of the active fins while a number of the at least one first dummy fin and a number of the at least one second dummy fin remain constant.

10. The method of claim 1 , wherein the forming at least one standard cell further includes,
forming conductive lines extending in the second direction, the conductive lines being parallel to one another in the first direction.

11. The method of claim 1 , wherein a conductivity type of the first active area is different from a conductivity type of the second active area.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Sang-Hoon
• Seo Jae-Woo
• Yang Gi-Young
• Lee Dal-Hee
• Cho Sung-Wee

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/00

  Computer-aided design [CAD] · CPC title

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F2119/18

  Manufacturability analysis or optimisation for manufacturability · CPC title