Data and clock signal voltages within an integrated circuit

Patent metadata

Field	Value
Publication number	US-9450571-B2
Application number	US-201414294593-A
Country	US
Kind code	B2
Filing date	Jun 3, 2014
Priority date	Jun 3, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14 . Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

First claim

We claim:

1. An integrated circuit comprising:
data processing circuitry configured to process a data signal passing along a data path within said data processing circuitry;
clocked circuitry coupled to said data processing circuitry and configured to regulate passage of said data signal along said data path under control of a clock signal;
data power supply circuitry coupled to said data processing circuitry and configured to supply power to said data processing circuitry; and
clock power supply circuitry coupled to said clocked circuitry and configured to supply power to said clocked circuitry;
wherein said data power supply circuitry and said clock power supply circuitry are configured such that, at least when said data processing circuitry is actively processing said data signal passing along said data path, said data signal has a data signal voltage amplitude and said clock signal has a clock signal voltage amplitude that is different from said data signal voltage amplitude,
wherein said data power supply circuitry is configured to operate in a plurality of modes having different associated data signal voltage amplitudes, and
wherein said clock power supply circuitry is configured to operate in a plurality of modes having different associated clock signal voltage amplitudes.

2. An integrated circuit as claimed in claim 1 , wherein said data signal has a voltage varying between a ground voltage level and a data supply voltage level and said clock signal has a voltage varying between said ground voltage level and a clock supply voltage level.

3. An integrated circuit as claimed in claim 1 , wherein said clock signal voltage amplitude is greater than said data signal voltage amplitude.

4. An integrated circuit as claimed in claim 2 , wherein a difference between said data supply voltage level and said ground voltage level is less than a difference between said clock supply voltage level and said ground voltage level.

5. An integrated circuit as claimed in claim 1 , wherein said data power supply circuitry is separate from said clock power supply circuitry.

6. An integrated circuit as claimed in claim 5 , wherein
said data power supply circuitry comprises a data power grid extending through said integrated circuit; and
said clock power supply circuitry comprises a clock power grid separate from said data power grid and extending through said integrated circuit.

7. An integrated circuit as claimed in claim 1 , wherein a difference between said data signal voltage amplitude and said clock signal voltage amplitude varies as said data signal voltage amplitude varies.

8. An integrated circuit as claimed in claim 7 , wherein said difference one of:
(i) increases monotonically as said data signal voltage amplitude increases;
(ii) decreases monotonically as said data signal voltage amplitude increases; and
(ii) varies non-monotonically as said data signal voltage amplitude increases.

9. An integrated circuit as claimed in claim 1 , wherein said data path extends between a plurality of data signal value capture and storage circuits, and said plurality of data value capture and storage circuits are controlled by said clock signal and operate synchronously with each other.

10. An integrated circuit as claimed in claim 9 , wherein said plurality of data signal value capture and storage circuits each comprise a plurality of transistors having respective gate inputs and said clock signal is supplied to said gate inputs.

11. An integrated circuit as claimed in claim 10 , wherein said gate inputs are part of one or more of:
(i) a transmission gate;
(ii) a tristate multiplexer;
(iii) a clock gated inverter; and
(iv) an inverter.

12. An integrated circuit as claimed in claim 10 , wherein within said plurality of data signal value capture and storage circuits said clock signal is supplied only to said gate inputs.

13. An integrated circuit as claimed in any one of claim 9 , wherein said plurality of data signal capture and storage circuits comprise a plurality of master slave latch circuits.

14. An integrated circuit as claimed in claim 1 , wherein said clock signal voltage amplitude differing from said data signal voltage amplitude serves to produce a different degree of variation in operation of said data processing circuitry and said clocked circuitry in dependence upon one or more of:
(i) manufacturing process variation;
(ii) operating voltage level variation; and
(iii) operating temperature variation.

15. An integrated circuit as claimed in claim 14 , wherein said degree of variation is less in said clocked circuitry than said data processing circuitry.

16. An integrated circuit comprising:
data processing circuitry configured to process a data signal passing along a data path within said data processing circuitry;
clocked circuitry coupled to said data processing circuitry and configured to regulate passage of said data signal along said data path under control of a clock signal;
data power supply circuitry coupled to said data processing circuitry and configured to supply power to said data processing circuitry;
clock power supply circuitry coupled to said clocked circuitry and configured to supply power to said clocked circuitry; and
one or more combinatorial logic circuits disposed within said data path between a plurality of data signal capture and storage circuits and configured to control a value of said data signal in dependence upon one or more further data signals,
wherein said data power supply circuitry and said clock power supply circuitry are configured such that, at least when said data processing circuitry is actively processing said data signal passing along said data path, said data signal has a data signal voltage amplitude and said clock signal has a clock signal voltage amplitude that is different from said data signal voltage amplitude, and
wherein said data path extends between said plurality of data signal value capture and storage circuits, and said plurality of data value capture and storage circuits are controlled by said clock signal and operate synchronously with each other.

17. An integrated circuit as claimed in claim 16 , further comprising one or more hold-time buffer circuits disposed in said data path and configured to increase a propagation time of said data signal along said data path without said value of said data signal having a dependence upon any further data signals.

18. An integrated circuit comprising:
data processing means for processing a data signal passing along a data path within said data processing means;
clocked means coupled to said data processing means for regulating passage of said data signal along said data path under control of a clock signal;
data power supply means coupled to said data processing means for supplying power to said data processing means; and
clock power supply means coupled to said clocked means for supplying power to said clocked means;
wherein said data power supply means and said clock power supply means operate such that, at least when said data processing means is actively processing said data signal passing along said data path, said data signal has a data signal voltage amplitude and said clock signal has a clock signal voltage amplitude that is different from said data signal voltage amplitude,
wherein said data power supply means is configured to operate in a plurality of modes having different associated data signal voltage amplitudes, and
wherein said clock power supply means is configured to operate in a plurality of modes having different as

Assignees

• Advanced Risc Mach Ltd

Inventors

• Frederick Jr Marlin Wayne
• Srivastava Ashwani Kumar

Classifications

• H03K5/02 Primary

  by amplifying (H03K5/04 takes precedence) · CPC title