Buffer circuit for buffering and settling input voltage to target voltage level and operation method thereof

Patent metadata

Field	Value
Publication number	US-9438215-B2
Application number	US-201414498623-A
Country	US
Kind code	B2
Filing date	Sep 26, 2014
Priority date	Mar 11, 2014
Publication date	Sep 6, 2016
Grant date	Sep 6, 2016

Abstract

A buffer circuit includes an amplifying unit suitable for comparing an input voltage of an input terminal with an output voltage of an output terminal, a current sinking unit suitable for controlling a sinking current of the amplifying unit when the input voltage is varied, and a current compensation unit suitable for uniformly maintaining a sinking current amount of the current sinking unit.

First claim

What is claimed is:

1. A buffer circuit, comprising:
an amplifying unit suitable for comparing an input voltage of an input terminal with an output voltage of an output terminal;
a current sinking unit suitable for controlling a sinking current of the amplifying unit when the input voltage is varied;
a current compensation unit suitable for uniformly maintaining a sinking current amount of the current sinking unit; and
a control signal generation unit suitable for receiving the input voltage to generate a control signal, which is activated when the input voltage is varied,
wherein the current sinking unit is controlled by the control signal.

2. The buffer circuit of claim 1 , wherein the current sinking unit comprises:
a first current sinking unit suitable for controlling the sinking current of the input terminal of the amplifying unit; and
a second current sinking unit coupled to the current compensation unit and suitable for controlling the sinking current of the output terminal of the amplifying unit.

3. The buffer circuit of claim 1 , wherein the control signal generation unit includes a detection circuit suitable for detecting a state of the input voltage.

4. The buffer circuit of claim 1 , wherein the amplifying unit comprises:
a driving unit suitable for comparing the output voltage of the output terminal with the input voltage of the input terminal and outputting a voltage, which is amplified according to a compared value, as the output voltage; and
an initial current sinking unit suitable for being driven based on a bias voltage applied from an external device.

5. The buffer circuit of claim 4 , wherein the driving unit comprises:
a comparison unit suitable for comparing the output voltage with the input voltage;
an output unit suitable for outputting the output voltage, which is amplified based on an output signal outputted from the comparison unit; and
a feedback unit suitable for providing a voltage level corresponding to the output voltage outputted from the output unit to the comparison unit.

6. The buffer circuit of claim 5 , wherein the initial current sinking unit comprises:
a first initial current sinking unit coupled to the comparison unit and suitable for controlling the sinking current of the comparison unit; and
a second initial current sinking unit coupled to the output unit and suitable for controlling the sinking current of the output unit.

7. The buffer circuit of claim 1 , wherein the current compensation unit includes a driving transistor, which is controlled by the output voltage of the output terminal.

8. The buffer circuit of claim 7 , wherein the driving transistor has a same size as a transistor for receiving the input voltage.

9. A buffer circuit, comprising:
an amplifying unit suitable for comparing an input voltage of an input terminal with an output voltage of an output terminal;
a current sinking unit coupled to the input terminal of the amplifying unit and suitable for controlling a sinking current of the amplifying unit when a power-up operation is performed;
a current compensation unit coupled to the output terminal of the amplifying unit and suitable for uniformly maintaining a sinking current amount of the current sinking unit; and
a control signal generation unit suitable for receiving the input voltage, the output voltage and a power-up signal, which is activated during the power-up operation, to generate a control signal activated during the power-up operation,
wherein the current sinking unit is controlled by the control signal.

10. The buffer circuit of claim 9 , wherein the current sinking unit comprises:
a first current sinking unit suitable for controlling the sinking current of the input terminal of the amplifying unit; and
a second current sinking unit coupled to the current compensation unit and suitable for controlling the sinking current of the output terminal of the amplifying unit.

11. The buffer circuit of claim 9 , wherein the control signal generation unit includes a level comparison unit suitable for comparing the voltage level of the output voltage with a reference input voltage, which is generated by increasing the input voltage by a predetermined level, and generating the control signal based on the output signal outputted from the level comparison unit or the power-up signal.

12. The buffer circuit of claim 9 , wherein the amplifying unit comprises:
a driving unit suitable for comparing the output voltage of the output terminal with the input voltage of the input terminal to output the output voltage; and
an initial current sinking unit suitable for being driven based on a bias voltage applied from an external device.

13. The buffer circuit of claim 12 , wherein the driving unit comprises:
a comparison unit suitable for comparing the output voltage with the input voltage;
an output unit suitable for outputting the output voltage, which is amplified based on an output signal outputted from the comparison unit; and
a feedback unit suitable for providing a voltage level corresponding to the output voltage outputted from the output unit to the comparison unit.

14. The buffer circuit of claim 12 , wherein the initial current sinking unit comprises:
a first initial current sinking unit coupled to the comparison unit and suitable for controlling the sinking current of the comparison unit; and
a second initial current sinking unit coupled to the output unit and suitable for controlling the sinking current of the output unit.

15. The buffer circuit of claim 9 , wherein the current compensation unit includes a driving transistor, which is controlled by the output voltage of the output terminal.

16. The buffer circuit of claim 15 , wherein the driving transistor has the same size as a transistor for receiving the input voltage.

17. The buffer circuit of claim 9 , wherein the input voltage is a fixed voltage.

Assignees

• Sk Hynix Inc

Inventors

• Lee Myung-Hwan

Classifications

• H03K5/02 Primary

  by amplifying (H03K5/04 takes precedence) · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title