Supply-modulation cross domain data interface

Patent metadata

Field	Value
Publication number	US-9509308-B2
Application number	US-201414502785-A
Country	US
Kind code	B2
Filing date	Sep 30, 2014
Priority date	Sep 30, 2014
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A method for converting data signals from one power supply voltage domain for use in another power supply voltage domain. The method includes receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain. The method also includes generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit. The method further includes communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal. The method also includes outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain. Other embodiments, such as an integrated circuit, and an input device, are also provided.

First claim

What is claimed is:

1. A method for communicating a data signal within an integrated circuit of a processing system having a first power supply voltage domain and a second power supply voltage domain, wherein at least one of a positive power supply voltage of the second power supply voltage domain and a negative power supply voltage of the second power supply voltage domain are modulated with respect to the first power supply voltage domain, the method comprising:
receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain;
generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit;
communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal; and
outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain, wherein generating the first intermediate differential signal comprises:
removing effects corresponding to modulation in at least one of the positive power supply voltage of the second power supply voltage domain and the negative power supply voltage of the second power supply voltage domain.

2. The method of claim 1 , wherein communicating the first intermediate differential signal to the first cross-coupled latch comprises communicating the first intermediate differential signal to the first cross-coupled latch that is coupled to the positive power supply voltage of the second power supply voltage domain.

3. The method of claim 2 , wherein:
the positive power supply voltage of the second power supply voltage domain does not drop below the positive power supply voltage of the first power supply voltage domain; and
the negative power supply voltage of the second power supply voltage domain does not drop below the negative power supply voltage of the first power supply voltage domain.

4. The method of claim 1 , wherein communicating the first intermediate differential signal to the first cross-coupled latch comprises communicating the first intermediate differential signal to the first cross-coupled latch that is coupled to the negative power supply voltage of the second power supply voltage domain.

5. The method of claim 4 , wherein:
the positive power supply voltage of the second power supply voltage domain does not rise above the positive power supply voltage of the first power supply voltage domain; and
the negative power supply voltage of the second power supply voltage domain does not rise above the negative power supply voltage of the first power supply voltage domain.

6. The method of claim 1 , wherein:
generating the first intermediate differential signal from the data signal comprises transmitting the data signal through a pair of alternating-current couplings to generate the first intermediate differential signal.

7. The method of claim 1 , wherein removing effects corresponding to at least one of the positive power supply voltage of the second power supply voltage domain and the negative power supply voltage of the second power supply voltage domain comprises:
communicating the data signal through a pair of cascode transistors coupled in series with a differential pair to generate the first intermediate differential signal.

8. A method for communicating a data signal within an integrated circuit of a processing system having a first power supply voltage domain and a second power supply voltage domain, wherein at least one of a positive power supply voltage of the second power supply voltage domain and a negative power supply voltage of the second power supply voltage domain are modulated with respect to the first power supply voltage domain, the method comprising:
receiving the data signal at a first node of the integrated circuit, wherein the first node is within the first power supply voltage domain;
generating a first intermediate differential signal from the data signal via a first conversion circuit of the integrated circuit;
communicating the first intermediate differential signal to a first cross-coupled latch, wherein the first cross-coupled latch generates a first output signal based on the first intermediate differential signal; and
outputting the first output signal from a second node of the integrated circuit, wherein the second node is in the second power supply voltage domain, wherein communicating the first intermediate differential signal to the first cross-coupled latch further comprises:
communicating the first intermediate differential signal to a first current mirror configured to generate a first current mirror signal based on the first intermediate differential signal; and
generating the first output signal based on the first current mirror signal.

9. The method of claim 8 , wherein communicating the first intermediate differential signal to the first cross-coupled latch further comprises:
communicating the first intermediate differential signal to a second current mirror configured to generate a second current mirror signal based on the first intermediate differential signal, wherein the second current mirror signal is a logical inverse of the first current mirror signal; and
communicating the first current mirror signal to a first inverter having a first output that is coupled, through a first resistor, to the second current mirror signal.

10. An integrated circuit comprising:
a first power supply voltage domain;
a second power supply voltage domain, wherein at least one of a positive power supply voltage of the second power supply voltage domain and a negative power supply voltage of the second power supply voltage domain are modulated with respect to the first power supply voltage domain; and
a cross-domain interface circuit, comprising:
a first conversion circuit that includes a first node and that is within the first power supply voltage domain, and
a second conversion circuit that is within the second power supply voltage domain and that includes a second node and a first cross-coupled latch,
wherein the first conversion circuit is configured to receive a data signal at the first node, generate a first intermediate differential signal from the data signal, and communicate the first intermediate differential signal to the second conversion circuit; and

wherein the second conversion circuit is configured to receive the first intermediate differential signal at the first cross-coupled latch, generate a first output signal based on the first intermediate differential signal via the first cross-coupled latch, and output the first output signal from the second node, wherein:
the second conversion circuit includes a first current mirror configured to generate a first current mirror signal based on the first intermediate differential signal, and
the second conversion circuit is configured to generate the first output signal based on the first current mirror signal.

11. The integrated circuit of claim 10 , wherein:
the first cross-coupled latch is coupled to a positive power supply voltage of the second power supply voltage domain.

12. The integrated circuit of claim 11 , wherein:
the positive power supply voltage of the second power supply voltage domain does not drop below the positive power supply voltage of the first power supply voltage domain; and
the negative power supply voltage of the second power supply voltage domain does not drop below the negative power supply voltage of the first power supply voltage domain.

Assignees

• Synaptics Inc

Inventors

• Lim Shao-Jen
• Shamarao Prashant

Classifications

• G06F3/044 Primary

  by capacitive means · CPC title

• G06F3/0416

  Control or interface arrangements specially adapted for digitisers · CPC title

• G06F2203/04103

  Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices · CPC title

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H03K5/02

  by amplifying (H03K5/04 takes precedence) · CPC title