Phase error compensation circuit

Patent metadata

Field	Value
Publication number	US-9479142-B1
Application number	US-201514806478-A
Country	US
Kind code	B1
Filing date	Jul 22, 2015
Priority date	Feb 25, 2015
Publication date	Oct 25, 2016
Grant date	Oct 25, 2016

Abstract

A method and system of compensating for phase error. A phase error compensation circuit is configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit includes a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal. A second transconductance circuit is configured to convert a voltage signal related to a Q input signal to a Q current signal. A first multiplier circuit is configured to multiply the Q current signal times a Q scaling constant. A second multiplier circuit is configured to multiply the I current signal times an I scaling constant. An I summer sums the I current signal with the scaled Q signal. A Q summer sums the Q current signal with the scaled I signal.

First claim

What is claimed is:

1. A phase error compensation circuit comprising:
a first transconductance circuit having a differential input and a differential output;
a second transconductance circuit having a differential input and a differential output;
a first multiplier circuit comprising:
a differential control input (V CI );
a second differential input coupled to the differential output of the first transconductance circuit; and
a differential output;

a second multiplier circuit comprising:
a differential control input (V CQ );
a second differential input coupled to the differential output of the second transconductance circuit; and
a differential output;

a first differential load comprising a first load and a second load, together having a differential input coupled to the differential output of the second multiplier circuit and sharing a common node; and
a second differential load comprising a first load and a second load together having a differential input coupled to the differential output of the first multiplier circuit and sharing the common node, wherein the first multiplier circuit is configured to multiply the differential current signal provided by the first transconductance circuit times a first scaling constant provided at the differential control input of the first multiplier circuit.

2. The phase error compensation circuit of claim 1 , wherein:
the first transconductance circuit is configured to convert a differential voltage signal at its differential input to a differential current signal at its differential output; and
the second transconductance circuit is configured to convert a differential voltage signal at its differential input to a differential current signal at its differential output.

3. The phase error compensation circuit of claim 2 , wherein each transconductance circuit comprises two transistors, the two transistors having a common node coupled to current source.

4. The phase error compensation circuit of claim 3 , wherein the two transistors of each transconductance circuit are bipolar transistors sharing a common emitter and have their respective collectors coupled to their corresponding multiplier circuit.

5. The phase error compensation circuit of claim 1 , wherein the second multiplier circuit is configured to multiply the differential current signal provided by the second transconductance circuit times a second scaling constant provided at the differential control input of the second multiplier circuit.

6. The phase error compensation circuit of claim 5 , wherein at least one of (i) the first scaling constant and (ii) the second scaling constant is substantially less than one.

7. The phase error compensation circuit of claim 1 , wherein the phase error compensation circuit is configured to generate a phase-corrected Q and I signals at a frequency of at least 1 GHz.

8. The phase error compensation circuit of claim 1 , wherein:
the first multiplier circuit comprises:
a first pair of transistors having a common node coupled to a first component of the differential output of the first transconductance circuit; and
a second pair of transistors having a common node coupled to a second component of the differential output of the first transconductance circuit; and

the second multiplier circuit comprises:
a first pair of transistors having a common node coupled to a first component of the differential output of the second transconductance circuit; and
a second pair of transistors having a common node coupled to a second component of the differential output of the second transconductance circuit.

9. The phase error compensation circuit of claim 8 , wherein the first and second pair of transistors of each multiplier circuit comprise bipolar transistors having an emitter area ratio of N, where N is greater than 1.

10. A phase error compensation circuit comprising:
a first transconductance circuit having a differential input and a differential output;
a second transconductance circuit having a differential input and a differential output;
a first multiplier circuit comprising:
a differential control input (V CI );
a second differential input coupled to the differential output of the first transconductance circuit; and
a differential output;

a second multiplier circuit comprising:
a differential control input (V CQ );
a second differential input coupled to the differential output of the second transconductance circuit; and
a differential output;

a first differential load comprising a first load and a second load, together having a differential input coupled to the differential output of the second multiplier circuit and sharing a common node;
a second differential load comprising a first load and a second load together having a differential input coupled to the differential output of the first multiplier circuit and sharing the common node; and a control circuit configured to provide control signals to the differential control input of the first and second multiplier circuit, respectively.

11. The phase error compensation circuit of claim 10 , wherein the control circuit comprises:
a first resistance element having a first node and a second node, wherein the first node is coupled to a reference bias voltage node;
a second resistance element having a first node and a second node, wherein the first node is coupled to the reference bias voltage node;
a first current source coupled to the second node of the first resistance element;
a second current source coupled to the second node of the second resistance element.

12. The phase error compensation circuit of claim 11 , wherein:
each multiplier circuit comprises a first pair of bipolar transistors and a second pair of bipolar transistors, wherein each pair of bipolar transistors has a common emitter;
each pair of bipolar transistors has a first bipolar transistor that has an emitter are that is N times the emitter area of a second bipolar transistor, where N is greater than 1;
the reference bias voltage node is coupled to a base of each first bipolar transistor of each multiplier circuit;
the second node of the first resistance element of the control circuit is coupled to each second bipolar transistor of the second multiplier circuit; and
the second node of the second resistance element of the control circuit is coupled to each second bipolar transistor of the first multiplier circuit.

13. The phase error compensation circuit of claim 1 , wherein:
the first differential load is configured to sum at least part of a current from the differential output of the second multiplier circuit with at least part of a current from the differential output of the first transconductance circuit, and
the second differential load is configured to sum at least part of a current from the differential output of the first multiplier circuit with at least part of a current from the differential output of the second transconductance circuit.

14. A phase error compensation circuit configured to generate a phase-corrected quadrature Q output signal and a corresponding phase-corrected in-phase I output signal, the circuit comprising:
a first transconductance circuit configured to convert a voltage signal related to an I input voltage signal to an I current signal;
a second transconductance circuit configured to convert a voltage signal related to a Q input voltage signal to a Q current signal;
a second multiplier circuit configured to multiply the Q current signal times a Q scaling constant to provide a scaled Q signal;
a first multiplier circuit configured to multiply the I current signal provided by the first transcondu

Assignees

• Linear Tech Corp

Inventors

• Myers John Perry

Classifications

• H03H11/22

  providing two or more phase shifted output signals, e.g. n-phase output · CPC title

• H03K5/02

  by amplifying (H03K5/04 takes precedence) · CPC title

• H03K5/26

  the characteristic being duration, interval, position, frequency, or sequence · CPC title

• H03H11/18 Primary

  Two-port phase shifters providing a predetermined phase shift, e.g. "all-pass" filters · CPC title

• H03K2005/00286

  Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency · CPC title