Method for manufacturing silicon carbide semiconductor device

Patent metadata

Field	Value
Publication number	US-9450068-B2
Application number	US-201314394115-A
Country	US
Kind code	B2
Filing date	Apr 10, 2013
Priority date	Apr 17, 2012
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

In a method for manufacturing a silicon carbide semiconductor device having a JFET, a trench is formed in a semiconductor substrate, and a channel layer and a second gate region are formed on an inner wall of the trench. The channel layer and the second gate region are planarized to expose a source region. A first recess deeper than a thickness of the source region is formed on both leading ends of the trench, and an activation annealing process of 1300° C. or higher is conducted in an inert gas atmosphere. A first conductivity type layer formed by the annealing process to cover a corner which is a boundary between a bottom and a side of the first recess is removed.

First claim

The invention claimed is:

1. A method for manufacturing a silicon carbide semiconductor device having a JFET, comprising:
preparing a semiconductor substrate including a first conductivity type substrate that is made of silicon carbide, a drift layer of a first conductivity type that is formed on the first conductivity type substrate by epitaxial growth, a first gate region of a second conductivity type that is formed on the drift layer by epitaxial growth, a source region of the first conductivity type that is formed on the first gate region by epitaxial growth or ion implantation;
forming a strip shaped trench having a longitudinal direction in one direction and penetrating through the source region and the first gate region to reach the drift layer;
forming a channel layer of the first conductivity type on an inner wall of the trench by epitaxial growth;
forming a second gate region of the second conductivity type on the channel layer;
planarizing the channel layer and the second gate region to expose the source region;
after the planarizing, conducting selective etching to remove at least the source region, the channel layer, and the second gate region on both leading ends of the trench, and forming a first recess deeper than a thickness of the source region on both the leading ends of the trench;
after the forming the first recess, conducting an activation annealing process at a temperature of 1300° C. or higher in an inert gas atmosphere;
removing a first conductivity type layer formed by the annealing process, the first conductivity type layer covering only a corner which is a boundary between a bottom and a side of the first recess; and
wherein the first conductivity type layer is formed by silicon carbide growth due to nitrogen in the inert gas atmosphere.

2. The method for manufacturing the silicon carbide semiconductor device having the JFET according to claim 1 , wherein
the removing of the first conductivity type layer includes etching a surface of the first conductivity type layer so that the first gate area is not completely removed at the bottom of the first recess while etching an overall surface of the semiconductor substrate including an interior of the first recess to a depth equal to or more than the thickness of the first conductivity type layer.

3. The method for manufacturing the silicon carbide semiconductor device having the JFET according to claim 1 , further comprising
forming an interlayer insulating film at a region including an interior of the first recess after the removing the first conductivity type layer.

4. The method for manufacturing the silicon carbide semiconductor device having the JFET according to claim 1 , further comprising:
forming a second recess deeper than the first gate region and reaching the drift layer in an outer peripheral region surrounding a cell region in which a cell of the JFFT is formed; and
forming a resurf layer of a second conductivity type within the drift layer so as to be disposed on a bottom of the second recess and a side of the second recess,
wherein after the forming the resurf layer, the activation annealing process is conducted, and when the first conductivity type layer is removed after the activation annealing process, another first conductivity type layer formed by the activation annealing process to cover a corner which is a boundary between the bottom and the side of the second recess is also removed.

5. The method for manufacturing the silicon carbide semiconductor device having the JFET according to claim 4 , wherein the second recess is formed adjacent to the first recess.

Assignees

• Denso Corp

Inventors

• Takeuchi Yuichi
• Sugiyama Naohiro

Classifications

• H10P95/906

  for altering the shape of semiconductors, e.g. smoothing the surface · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P32/172

  being crystalline silicon carbide · CPC title

• H10D84/035

  using silicon carbide [SiC] technology · CPC title