System and method for bit-wise selective masking of scan vectors for X-value tolerant built-in self test

Patent metadata

Field	Value
Publication number	US-9448282-B1
Application number	US-201414179299-A
Country	US
Kind code	B1
Filing date	Feb 12, 2014
Priority date	Feb 12, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

A system and method are provided for selective bit-wise masking of X-values in scan channels in an integrated circuit (IC) during a built-in self test (BIST). The composite mask pattern is selectively generated according to locations of X-values identified in a simulation of the IC. The composite mask pattern is stored on the IC and cyclically maintained while being applied to the operational scan results of the IC. The composite mask pattern is recycled over a plurality of scan iterations to effectively prevent the X-values from influencing the resulting signature of the BIST that represents a functional fingerprint of the IC and minimize storage requirements for the composite mask pattern.

First claim

What is claimed is:

1. A built in self test system incorporated in an integrated circuit (IC), the system having mask pattern storage on the IC, the system comprising:
a test controller executing a plurality of scan iterations on operational portions of the IC to generate a plurality of bits representing operational scan results from a scan iteration;
at least one scan vector unit maintaining the plurality of bits representing the operational scan results from a scan iteration;
at least one internal mask vector unit actuated for cyclically maintaining a composite mask pattern formed by a plurality of values set for a series of bit-wise masking locations, the set values of the bit-wise masking locations being cyclically sequenced for application to the plurality of scan iterations of the IC, the composite mask pattern being sized no greater than the plurality of bits representing the operational scan results of a single scan iteration;
masking circuitry actuated for logically combining a received bit-wise masking location value from the composite mask pattern with a corresponding received one of the plurality of bits representing the operational scan results; and,
a circuit signature unit coupled to the masking circuitry executed to generate a signature representing the operational scan results.

2. The system as recited in claim 1 , wherein the composite mask pattern is sized to be equivalent to the plurality of bits representing the operational scan results of a single scan iteration.

3. The system as recited in claim 1 , wherein the composite mask pattern is sized to be of an evenly-divided portion of the plurality of bits representing the operational scan results of a single scan iteration.

4. The system as recited in claim 1 , wherein the series of bit-wise masking location values of the internal mask vector unit are selectively set to indicate X-values pre-identified in the plurality of bits representing operational scan results in the at least one scan vector unit.

5. The system as recited in claim 1 , wherein the masking circuitry includes a masking logic network.

6. The system as recited in claim 5 , wherein the masking logic network includes a plurality of logic gates, each coupled with a respective scan vector unit and the internal mask vector unit for selectively masking the plurality of bits representing the operational scan results with the composite mask pattern to quarantine X-values from reaching the circuit signature unit.

7. The system as recited in claim 6 , further comprising:
a plurality of scan vector units, each maintaining a plurality of bits representing operational scan results from a scan iteration; and,
a plurality of internal mask vector units, each maintaining a composite mask pattern therein, the plurality of internal mask vector units being selectively applied to the plurality of scan vector units according to a predetermined set of factors including the locations of X-values in each scan vector unit.

8. The system as recited in claim 7 , wherein the masking logic network further comprises a plurality of sequential memory units with at least one operably coupled to each scan vector unit to selectively apply at least one composite mask pattern thereto.

9. The system as recited in claim 8 , wherein a plurality of flip flops are operably coupled to each scan vector unit to selectively apply at least one of:
a first composite mask pattern;
a second composite mask pattern;
a combination of the first and second composite mask patterns; and,
no masking.

10. The system as recited in claim 9 , wherein the circuit signature unit includes a multiple input shifting register and the internal mask vector units each include a shifting register.

11. The system as recited in claim 10 , wherein the internal mask vector units each include a feedback channel to feedback a bit output from a least significant bit position to the most significant bit position and correspondingly shift others of the plurality of bits representing the composite mask pattern to less significant bit positions to cyclically maintain the respective composite mask pattern in registration with the plurality of scan vector units.

12. The system as recited in claim 1 , wherein the internal mask vector unit includes a feedback channel to feedback a bit output from a least significant bit position to the most significant bit position and correspondingly shift others of the plurality of bits representing the composite mask pattern to less significant bit positions to cyclically maintain the respective composite mask pattern in registration with the plurality of scan vector units.

13. The system as recited in claim 1 , further comprising a pseudo random pattern generator (PRPG) disposed on the IC and coupled to the test controller to provide a plurality of pseudo random input patterns to the IC.

14. A method for generating a composite mask pattern for Built In Self Test (BIST) of an Integrated Circuit (IC), the method comprising:
receiving a digital representation of an integrated circuit (IC) having a built in self test controller including at least an internal mask vector unit, masking circuitry, a scan vector unit, and a circuit signature unit;
executing a processing unit to simulate operation of the IC executing a plurality of scan iterations on operational portions of the IC to generate a plurality of bits representing operational scan results from a scan iteration, the operational scan results being maintained in the scan vector unit;
identifying bitwise locations of the scan vector unit storing X-values of the operational scan results therein for each of the plurality of scan iterations;
generating a composite mask pattern having a bit length no greater than the plurality of bits representing the operational scan results of a single scan iteration, the composite mask pattern formed by a plurality of values set for a series of bit-wise masking locations, each of the bit-wise masking location values of the composite mask pattern being set according to the identified locations of X-values in the scan vector unit for the plurality of scan iterations of the IC; and
applying the composite mask pattern to adaptively mask for the identified X-values of the scan vector unit to normalize an operational circuit signature to be substantially devoid of X-values, the adaptive masking by logically combining a received bit-wise masking location value from the composite mask pattern with a corresponding received one of the plurality of bits representing the operational scan results, the set values of the bit-wise masking locations being cyclically sequenced for said logical combination.

15. The method as recited in claim 14 , wherein the composite mask pattern is maintained in cyclical bitwise registration with at least a portion of the operational scan results in the scan vector unit, the mask vector unit recycling masking bit values for masking of the operational scan results.

16. The method as recited in claim 15 , further comprising generating a plurality of composite mask patterns according to the identified locations of X-values in the operational scan results.

17. The method as recited in claim 16 , further comprising selectively applying the plurality of composite mask patterns to the scan vector unit according to the identified locations of X-values in the operational scan results.

18. A method for built in self test incorporated in an integrated circuit (IC), the IC having mask pattern storage on the IC, the method comprising:
actuating a test controller to execute a plura

Assignees

• Cadence Design Systems Inc

Inventors

• Meehl Dale Edward

Classifications

• G01R31/318335 Primary

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title

• G01R31/318547

  Data generators or compressors · CPC title

• G01R31/318563

  Multiple simultaneous testing of subparts · CPC title

• G01R31/31703

  Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193) · CPC title

• G01R31/318566

  Comparators; Diagnosing the device under test · CPC title