Method and apparatus for test time reduction using fractional data packing

Patent metadata

Field	Value
Publication number	US-9448284-B2
Application number	US-201414272760-A
Country	US
Kind code	B2
Filing date	May 8, 2014
Priority date	May 8, 2014
Publication date	Sep 20, 2016
Grant date	Sep 20, 2016

Abstract

An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

First claim

What is claimed is:

1. A circuit comprising:
an input converter configured to receive N scan inputs and configured to generate M pseudo scan inputs, where M and N are integers;
a scan compression architecture coupled to the input converter and configured to generate P pseudo scan outputs in response to the M pseudo scan inputs; and
an output converter coupled to the scan compression architecture and configured to generate Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers, and the input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency, and a ratio of the first frequency and the second frequency is equal to a ratio of M and N and to a ratio of P and Q.

2. The circuit of claim 1 further comprising a monitor configured to receive a scan clock and generate an internal clock, wherein the scan compression architecture is configured to be driven by the internal clock at the second frequency.

3. The circuit of claim 2 , wherein the monitor is configured to receive a status signal from the input converter, the status signal configured to update the monitor on a number of scan inputs stored in the input converter at a beginning of every scan clock.

4. The circuit of claim 2 , wherein the monitor is configured to discontinue the internal clock to the scan compression architecture when the number of scan inputs stored in the input converter, at the beginning of the scan clock, is less than M.

5. The circuit of claim 2 , wherein the output converter is configured to receive an enable signal from the monitor, the enable signal configured to disable the storage of pseudo scan outputs in the output converter when the pseudo scan outputs are not received in the output converter.

6. The circuit of claim 1 , wherein the input converter is configured to receive the N scan inputs at every scan clock and configured to generate the M pseudo scan inputs at the second frequency.

7. The circuit of claim 1 , wherein the input converter and the output converter are configured to store the N scan inputs and the P pseudo scan outputs respectively.

8. The circuit of claim 1 , wherein the scan compression architecture further comprises:
a decompressor coupled to the input converter and configured to receive the M pseudo scan inputs;
a compressor coupled to the decompressor and configured to generate the P pseudo scan outputs; and
a plurality of scan chains coupled between the decompressor and the compressor, wherein each scan chain of the plurality of scan chains comprises a plurality of scan cells.

9. The circuit of claim 8 , wherein the plurality of scan chains is driven by the internal clock.

10. The circuit of claim 8 , wherein the decompressor is configured to generate a plurality of core scan inputs in response to the M pseudo scan inputs.

11. The circuit of claim 8 , wherein the plurality of scan chains is configured to receive the plurality of core scan inputs, wherein each scan cell of the plurality of scan cells is configured to shift a core scan input of the plurality of core scan inputs at the second frequency.

12. The circuit of claim 8 wherein the plurality of scan chains is configured to generate a plurality of core scan outputs in response to the plurality of core scan inputs.

13. The circuit of claim 8 , wherein the compressor is configured to generate the P pseudo scan outputs in response to the plurality of core scan outputs.

14. The circuit of claim 1 , wherein a storage depth of the input converter is K bits, where K is an integer and K is greater than or equal to 2N and a storage depth of the output converter is L bits, wherein L is an integer and L is greater than or equal to 2P.

Assignees

• Texas Instruments Inc

Inventors

• Potty Sreenath Narayanan
• Mittal Rajesh
• Kawoosa Mudasir Shafat
• Singhal Vivek

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/3183

  Generation of test inputs, e.g. test vectors, patterns or sequences · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/318335 Primary

  Test pattern compression or decompression (compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921) · CPC title

• G01R31/318563

  Multiple simultaneous testing of subparts · CPC title