Programmable test compression architecture input/output shift register coupled to sci/sco/pco

Patent metadata

Field	Value
Publication number	US-2016252574-A1
Application number	US-201615151035-A
Country	US
Kind code	A1
Filing date	May 10, 2016
Priority date	Jun 11, 2009
Publication date	Sep 1, 2016
Grant date	—

Abstract

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

First claim

What is claimed is:

1 . A programmable access test compression architecture comprising:
(a) functional circuitry having test stimulus inputs and test response outputs; (b) scan path circuits, each scan path circuit having a scan input, a scan output, a clock input, a scan enable input, stimulus outputs coupled to the stimulus inputs of the functional logic, and response inputs coupled to the response outputs of the functional logic; (c) decompressor circuitry having parallel compressed data inputs and having outputs connected to the scan inputs of the scan path circuits; (d) compactor circuitry having inputs connected to the scan outputs of the scan path circuits and having parallel compressed data outputs; (e) a scan clock input coupled to the scan path circuits, the decompressor circuitry, and the compressor circuitry; (f) a scan enable input coupled to the scan path circuits, the decompressor circuitry, and the compressor circuitry; and (g) an input/output shift register having a serial compressed data input, a serial compressed data output, parallel inputs coupled to the parallel compressed data outputs, parallel outputs coupled to the parallel compressed data inputs of the decompressor circuitry, and a shift clock input.

2 . The programmable access test compression architecture of claim 1 in which the shift clock input is connected to the scan enable input.

Assignees

• Texas Instruments Inc

Inventors

• Whetsel Lee D

Classifications

• G01R31/3172

  Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/31727

  Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks (G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922) · CPC title

• G01R31/31723

  Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes (routing the test signal to or from the device under test G01R31/31926) · CPC title

• G01R31/318547 Primary

  Data generators or compressors · CPC title