Wiring substrate

Patent metadata

Field	Value
Publication number	US-9431333-B2
Application number	US-201514753203-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Jul 4, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

A wiring substrate includes a wiring layer. Metal posts are arranged on the wiring layer. The metal posts are used to mount an electronic component. A protective layer covers a surface of the wiring layer on which the metal posts are arranged. The wiring layer includes a seed layer and a metal plating layer. The metal plating layer has a size that is the same as that of the seed layer in a plan view. The metal posts each include an upper end, which projects from the protective layer, and a lower end, which has a width that is the same as that of the upper end or greater. The protective layer includes a fillet for each metal post. The fillet extends toward an upper end surface of the corresponding metal post and contacts a side surface of the corresponding metal posts.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a wiring layer;
metal posts arranged on the wiring layer, wherein the metal posts are used to mount an electronic component; and
a protective layer that covers a surface of the wiring layer on which the metal posts are arranged;
wherein the wiring layer includes a seed layer and a metal plating layer formed on the seed layer, wherein the metal plating layer has a size that is the same as a size of the seed layer in a plan view;
the metal posts each include an upper end, which projects from the protective layer, and a lower end, which is buried in the protective layer and has a width that is the same as or greater than a width of the upper end; and
the protective layer includes a fillet for each of the metal posts, wherein the fillet extends toward an upper end surface of a corresponding one of the metal posts and contacts a side surface of the corresponding one of the metal posts,
wherein each of the metal posts has a cylindrical shape or a polygonal rod shape,
surfaces of the wiring layer and the surfaces of the metal posts are roughened,
the roughened surfaces of the wiring layer and the surfaces of the metal posts have a greater roughness than the surface of the wiring layer on which the metal posts are arranged.

2. The wiring substrate according to claim 1 , further comprising a surface-processed layer that covers the upper end surface of each of the metal posts.

3. The wiring substrate according to claim 1 , wherein a roughness of the roughened surfaces of the wiring layer and the surfaces of the metal posts is in the range of 100 to 500 μm.

4. The wiring substrate according to claim 1 , wherein each of the metal posts is a plated metal and is coupled to an upper surface of the metal plating layer.

5. The wiring substrate according to claim 1 , wherein the wiring layer includes
two adjacent portions, on which two metal posts of the metal posts are respectively arranged, and
a wire that is formed between the two adjacent portions of the wiring layer.

6. The wiring substrate according to claim 1 , wherein:
the wiring layer is a first one of a plurality of wiring layers; and
the first wiring layer includes a first wire that is connected to a second one of the plurality of wiring layers, and a second wire that is not connected to the second wiring layer.

7. A wiring substrate comprising:
a wiring layer;
metal posts arranged on the wiring layer, wherein the metal posts are used to mount an electronic component; and
a protective layer that covers a surface of the wiring layer on which the metal posts are arranged;
wherein the wiring layer includes a seed layer and a metal plating layer formed on the seed layer, wherein the metal plating layer has a size that is the same as a size of the seed layer in a plan view;
the metal posts each include an upper end, which projects from the protective layer, and a lower end, which is buried in the protective layer and has a width that is the same as or greater than a width of the upper end; and
the protective layer includes a fillet for each of the metal posts, wherein the fillet extends toward an upper end surface of a corresponding one of the metal posts and contacts a side surface of the corresponding one of the metal posts,
the wiring substrate further comprising an insulation layer formed on a surface of the wiring layer opposite to the surface on which the metal posts are arranged,
wherein the protective layer includes an opening that exposes a portion of an upper surface of the insulation layer.

8. The wiring substrate according to claim 7 , further comprising a surface-processed layer that covers the upper end surface of each of the metal posts.

9. The wiring substrate according to claim 7 , wherein a surface of each of the metal posts is roughened.

10. The wiring substrate according to claim 7 , wherein:
the wiring substrate includes a batch of singulated wiring substrates; and
the opening is positioned at a corner of each of the singulated wiring substrates.

11. The wiring substrate according to claim 7 , wherein:
the wiring substrate includes a batch of singulated wiring substrates; and
the opening is positioned at a cutting location between two adjacent singulated wiring substrates of the singulated wiring substrates.

12. A wiring substrate comprising:
a wiring layer;
metal posts arranged on the wiring layer, wherein the metal posts are used to mount an electronic component; and
a protective layer that covers a surface of the wiring layer on which the metal posts are arranged;
wherein the wiring layer includes a seed layer and a metal plating layer formed on the seed layer, wherein the metal plating layer has a size that is the same as a size of the seed layer in a plan view;
the metal posts each include an upper end, which projects from the protective layer, and a lower end, which is buried in the protective layer and has a width that is the same as or greater than a width of the upper end; and
the protective layer includes a fillet for each of the metal posts, wherein the fillet extends toward an upper end surface of a corresponding one of the metal posts and contacts a side surface of the corresponding one of the metal posts,
wherein:
the wiring layer includes a first wire, on which the metal posts are arranged, and a second wire that is free from the metal posts; and
the protective layer includes an opening that exposes a portion of an upper surface of the second wire.

13. The wiring substrate according to claim 12 , further comprising a surface-processed layer that covers the upper end surface of each of the metal posts.

14. The wiring substrate according to claim 12 , wherein a surface of each of the metal posts is roughened.

15. The wiring substrate according to claim 12 , wherein the portion of the upper surface of the second wire functions as a connection pad.

16. The wiring substrate according to claim 12 , wherein the portion of the upper surface of the second wire has one or more of an alignment mark, a mark that indicates a serial number, and a mark that indicates a type of the wiring substrate.

Assignees

• Shinko Electric Ind Co

Inventors

• Rokugawa Takahiro

Classifications

• H05K1/11 Primary

  Printed elements for providing electric connections to or between printed circuits · CPC title

• H05K2201/09818

  Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809 · CPC title

• H05K2203/0723

  Electroplating, e.g. finish plating · CPC title

• H05K3/40

  Forming printed elements for providing electric connections to or between printed circuits · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title