Methods, apparatus, and articles of manufacture to group design stages in design space optimization of semiconductor design for tool agnostic design flows
US-2024330559-A1 · Oct 3, 2024 · US
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Nimmagadda Narendra patents
Nimmagadda Narendra is listed as an inventor on 4 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Nimmagadda Narendra |
| Total patents | 4 |
| First publication | Oct 27, 2015 |
| Latest publication | Oct 3, 2024 |
Notable patents
Publications ranked by popularity score, then publication date.
Fixing of semiconductor hold time
US-9430608-B2 · Aug 30, 2016 · US
Fixing of semiconductor hold time
US-2016042117-A1 · Feb 11, 2016 · US
Semiconductor hold time fixing
US-9171112-B2 · Oct 27, 2015 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Synopsys Inc | 3 |
| Intel Corp | 1 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F30/392 | 4 |
| G06F30/398 | 3 |
| G06F30/3312 | 3 |
| G06F30/394 | 3 |
| G06F30/396 | 3 |