Tunnel field-effect transistor

Patent metadata

Field	Value
Publication number	US-9419114-B2
Application number	US-201514599354-A
Country	US
Kind code	B2
Filing date	Jan 16, 2015
Priority date	Jan 17, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.

First claim

What is claimed is:

1. A tunnel field-effect transistor device, comprising:
a semiconductor substrate;
a fin structure contacting the semiconductor substrate on a major surface of the semiconductor substrate, wherein the fin structure is an elevated structure with respect to the semiconductor substrate, wherein the fin structure has a height measured in a direction orthogonal to the major surface of the semiconductor substrate, wherein the fin structure has a length measured in a longitudinal direction parallel to the major surface, wherein the fin structure has a width measured in a direction orthogonal to both the direction of the height and the longitudinal direction, the fin structure comprising a channel region, a drain region, and a source region, wherein the source region is disposed on the channel region, wherein the source region comprises a gate interface portion wherein the channel region is disposed on the drain region, and wherein the source region and the drain region are of opposite conductivity type;
a pocket layer covering the gate interface portion of the source region, the pocket layer contacting at least part of the channel region, wherein the gate interface portion of the source region comprises at least three mutually non-coplanar surface segments;
a gate dielectric layer covering the pocket layer, the gate dielectric layer electrically isolating the gate electrode and the source region: and
a gate electrode covering the gate dielectric layer, wherein the gate electrode is substantially parallel to the at least three non-coplanar surface segments, wherein the pocket layer comprises an intrinsic semiconductor material or is doped with a species opposite a conductivity type of the source region, wherein the pocket layer is configured to capture charge carriers tunneling from the source region in a direction of the gate electrode, and wherein the pocket layer is configured to divert the charge carriers via the channel region to a portion of the drain region which is in contact with the channel region but which is electrically insulated from the source region.

2. The tunnel field-effect transistor device of claim 1 , wherein each of the at least three mutually non-coplanar surface segments are oriented orthogonal or parallel to the major surface of the semiconductor substrate contacting the fin structure.

3. The tunnel field-effect transistor device of claim 1 , wherein the gate interface portion comprises an end portion of the source region with respect to a longitudinal direction along which the fin structure extends over the semiconductor substrate.

4. The tunnel field-effect transistor device of claim 3 , further comprising a source contact configured for providing an electrical interface to the source region, a drain contact configured for providing an electrical interface to the drain region and a gate contact configured for providing an electrical interface to the gate electrode, wherein the source contact is disposed between the drain contact and the gate contact along the longitudinal direction.

5. The tunnel field-effect transistor device of claim 3 , further comprising a source contact for providing an electrical interface to the source region, wherein the source contact is at least partially surrounded by the gate electrode.

6. The tunnel field-effect transistor device of claim 1 , wherein the gate interface portion comprises a central portion of the source region with respect to a longitudinal direction along which the fin structure extends over the semiconductor substrate, and wherein the gate interface portion does not comprise an end portion of the source region with respect to the longitudinal direction.

7. The tunnel field-effect transistor device of claim 6 , further comprising a source contact configured for providing an electrical interface to the source region, a drain contact configured for providing an electrical interface to the drain region and a gate contact configured for providing an electrical interface to the gate electrode, wherein the gate contact is disposed between the source contact and the drain contact along the longitudinal direction.

8. The tunnel field-effect transistor device of claim 1 , wherein the gate interface portion comprises an end portion of the source region with respect to a longitudinal direction along which the fin structure extends over the semiconductor substrate.

9. The tunnel field-effect transistor device of claim 8 , further comprising a source contact configured for providing an electrical interface to the source region, a drain contact configured for providing an electrical interface to the drain region and a gate contact configured for providing an electrical interface to the gate electrode, wherein the source contact is disposed between the drain contact and the gate contact along the longitudinal direction.

10. The tunnel field-effect transistor device of claim 8 , further comprising a source contact for providing an electrical interface to the source region, wherein the source contact is at least partially surrounded by the gate electrode.

11. The tunnel field-effect transistor device of claim 1 , wherein the gate interface portion comprises a central portion of the source region with respect to a longitudinal direction along which the fin structure extends over the semiconductor substrate, and wherein the gate interface portion does not comprise an end portion of the source region with respect to the longitudinal direction.

12. The tunnel field-effect transistor device of claim 11 , further comprising a source contact configured for providing an electrical interface to the source region, a drain contact configured for providing an electrical interface to the drain region and a gate contact configured for providing an electrical interface to the gate electrode, wherein the gate contact is disposed between the source contact and the drain contact along the longitudinal direction.

13. The tunnel field-effect transistor device of claim 1 , configured to avoid or reduce traverse tunneling or point tunneling.

14. The tunnel field-effect transistor device of claim 1 , wherein the gate interface portion of the source region comprises four mutually non-coplanar surface segments, and wherein a gate is deposited on one side of the fin structure, whereby area tunneling can be achieved via the four mutually non-coplanar surface segments.

15. The tunnel field-effect transistor device of claim 1 , further comprising a source contact configured for providing an electrical interface to the source region, a drain contact configured for providing an electrical interface to the drain region, and a gate contact configured for providing an electrical interface to the gate electrode, wherein the gate interface portion of the source region comprises four mutually non-coplanar surface segments, and wherein the source contact is disposed between the drain contact and the gate contact along the longitudinal direction parallel to the major surface, whereby tunneling can occur via the four mutually non-coplanar surface segments.

16. The tunnel field-effect transistor device of claim 15 , further comprising spacers provided along a gate and source-channel region side wall, wherein the spacers are configured to allow silicidation to be carried out simultaneously for the gate contact, the source contact, and the drain contact, and wherein the spacers comprise a SiN material.

17. The tunnel field-effect transistor device of claim 1 , wherein the pocket is doped so as to achieve a tuning of a tunneling onset voltage.

18. Th

Assignees

• Imec Vzw
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Walke Amey Mahadev
• Vandooren Anne
• Bhuwalka Krishna Kumar

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10D64/01302

  the insulator being formed after the semiconductor body, the semiconductor being silicon · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title