Methods for producing a tunnel field-effect transistor

Patent metadata

Field	Value
Publication number	US-9390975-B2
Application number	US-201514591228-A
Country	US
Kind code	B2
Filing date	Jan 7, 2015
Priority date	Jan 20, 2005
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

A method for producing a tunnel field-effect transistor is disclosed. Connection regions of different doping types are produced by means of self-aligning implantation methods.

First claim

What is claimed is:

1. A method of forming an integrated circuit comprising a tunnel transistor, the method comprising:
forming an auxiliary layer over a substrate;
forming at least one auxiliary region by patterning the auxiliary layer and removing material of the auxiliary layer;
forming a first spacer element in a region in which material of the auxiliary layer has been removed;
doping a first connection region having a first doping type of a transistor, the first spacer element and the auxiliary region serving as a mask;
covering the first connection region with a covering material;
removing material of the auxiliary region;
forming a second spacer element in a region in which material of the auxiliary region has been removed;
doping a second connection region having a second doping type of the transistor, the first doping being opposite the second doping type, the second spacer element and the covering material serving as a mask; and
forming an extension region in only one of the first connection region or the second connection region but not the other one of the first connection region or the second connection region.

2. The method of claim 1 , wherein patterning the auxiliary layer comprises forming a trench having two sidewalls facing one another.

3. The method of claim 2 , wherein a minimum lateral dimension of the trench is less than 500 nanometers.

4. The method of claim 1 , wherein a control region of the transistor is formed after removing material of the auxiliary region.

5. The method of claim 1 , wherein forming the extension region comprises performing an additional doping step.

6. The method of claim 1 , further comprising performing a silicidation process wherein only one of the first connection region or the second connection region is silicided, wherein the silicidation process is suppressed on the other one of the first connection region or the second connection region.

7. A method of forming an integrated circuit comprising a tunnel transistor, the method comprising:
forming an auxiliary layer over a substrate;
forming at least one auxiliary region by patterning the auxiliary layer and removing material of the auxiliary layer;
forming a first spacer element in a region in which material of the auxiliary layer has been removed;
doping a first connection region having a first doping type of a transistor, the first spacer element and the auxiliary region serving as a mask;
covering the first connection region with a covering material;
removing material of the auxiliary region;
forming a control region of the transistor, wherein the control region of the transistor is produced before forming the first spacer element;
forming a second spacer element in a region in which material of the auxiliary region has been removed; and
doping a second connection region having a second doping type of the transistor, the first doping being opposite the second doping type, the second spacer element and the covering material serving as a mask.

8. The method of claim 7 , wherein the first connection region and the second connection region form input/output nodes of the tunnel transistor.

9. A method of forming an integrated circuit comprising a tunnel transistor, the method comprising:
forming an auxiliary layer over a substrate;
forming a structured auxiliary layer having sidewalls by patterning the auxiliary layer, wherein forming the structured auxiliary layer comprises forming a projection having two sidewalls facing away from one another;
forming a first spacer on the sidewalls of the structured auxiliary layer;
forming a first connection region of a first doping type in the substrate using the first spacer and the structured auxiliary layer as a mask;
covering the first connection region with a covering material;
forming an opening by removing the structured auxiliary layer;
forming a second spacer in the opening; and
forming a second connection region of a second doping type in the substrate, the second spacer and the covering material as a mask, the second doping type being opposite to the first doping type, the first connection region and the second connection region being part of the tunnel transistor.

10. The method of claim 9 , wherein forming a first spacer comprises forming a first layer of a semi-conductive or conductive material and forming a second layer of an insulating material over the first layer, the first layer being a control region of the transistor.

11. The method of claim 9 , wherein the first connection region and the second connection region form input/output nodes of the tunnel transistor.

Assignees

• Infineon Technologies Ag

Inventors

• Kakoschke Ronald
• Tews Helmut Horst

Classifications

• H10D64/0133

  at least part of the entire electrode being a sidewall spacer, being formed by transformation under a mask or being formed by plating at a sidewall · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title