Reconfigurable tunnel field-effect transistors

Patent metadata

Field	Value
Publication number	US-9293467-B2
Application number	US-201414489949-A
Country	US
Kind code	B2
Filing date	Sep 18, 2014
Priority date	Sep 30, 2013
Publication date	Mar 22, 2016
Grant date	Mar 22, 2016

Abstract

A tunnel field-effect transistor (TFET) device includes first and second semiconductor contact regions separated by a semiconductor channel region; a channel gate overlying the channel region; and first and second doping gates overlying the first and second contact regions respectively; wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region.

First claim

The invention claimed is:

1. A tunnel field-effect transistor (TFET) device, comprising:
first and second semiconductor contact regions separated by a semiconductor channel region;
a channel gate overlying the channel region; and
first and second doping gates overlying the first and second contact regions respectively; and
further comprising first and second contact electrodes connected to the first and second contact regions respectively, wherein at least one of the first and second doping gates is shorted to the corresponding contact electrode, and
wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region.

2. The TFET device of claim 1 , wherein the channel region is configured such that formation of a tunnel junction results from application of a bias voltage to the channel gate.

3. The TFET device of claim 1 , wherein the channel region is configured such that, on application of the positive and negative voltage levels to the doping gates, a tunnel junction exists when no bias voltage is applied to the channel gate.

4. The TFET device of claim 1 , wherein each of the contact regions comprises a substantially undoped semiconductor.

5. The TFET device of claim 1 , wherein the channel region and the contact regions are formed from the same semiconductor.

6. The TFET device of claim 1 , wherein the channel region and the contact regions are formed in a heterostructure.

7. The TFET device of claim 1 , wherein each of the doping gates is shorted to the corresponding contact electrode.

8. The TFET device of claim 1 , wherein the channel region and the contact regions are formed in a nanostructure.

9. The TFET device of claim 8 , wherein the nanostructure comprises a nanowire.

10. The TFET device of claim 8 , wherein the channel region and the contact regions are formed in a planar nanostructure.

11. A static random access memory (SRAM) cell, comprising:
a pair of access transistors, each of which is connected to a respective signal line configured to control read and write operations, wherein each access transistor comprises a tunnel field-effect transistor (TFET) device, with each TFET device further comprising first and second semiconductor contact regions separated by a semiconductor channel region, a channel gate overlying the channel region, and first and second doping gates overlying the first and second contact regions respectively, wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region; and
wherein one of the contact regions for each access transistor is connected to the respective signal line.

12. The SRAM cell of claim 11 , wherein, for each TFET access device, the doping gate overlying the contact region connected to the respective signal line is shorted to that signal line.

13. The SRAM cell of claim 12 , wherein the doping gate overlying the other contact region in the TFET access device is connected to receive the inversion of any signal applied to the signal line.

14. The SRAM cell of claim 13 , wherein the storage cell further comprises a pair of cross-coupled inverters, each inverter including a p-type TFET device and an n-type TFET device.

15. The SRAM cell of claim 12 , wherein the contact regions of each TFET access device are biased independently of the doping gates.

16. A static random access memory (SRAM) device, comprising:
a plurality of SRAM cells electrically connected between pairs of word lines and bit lines;
each SRAM cell further comprising a pair of cross-coupled inverters and a pair of access transistors, each access transistor connected to a respective signal line configured to control read and write operations, wherein each access transistor comprises a tunnel field-effect transistor (TFET) device, with each TFET device further comprising first and second semiconductor contact regions separated by a semiconductor channel region, a channel gate overlying the channel region, and first and second doping gates overlying the first and second contact regions respectively, wherein application of a positive voltage level at the first doping gate and a negative voltage level at the second doping gate produces an n-type first contact region and a p-type second contact region, and reversing the voltage levels at the doping gates produces a p-type first contact region and an n-type second contact region; and
wherein one of the contact regions for each access transistor is connected to the respective signal line.

17. The SRAM device of claim 16 , wherein, for each TFET access device, the doping gate overlying the contact region connected to the respective signal line is shorted to that signal line.

18. The SRAM device of claim 16 , wherein the doping gate overlying the other contact region in the TFET access device is connected to receive the inversion of any signal applied to the signal line.

19. The SRAM device of claim 16 , wherein each pair of cross-coupled inverters comprises a p-type TFET device and an n-type TFET device.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Moselund Kirsten E
• Riel Heike E

Classifications

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D62/123

  comprising junctions · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D12/211

  Gated diodes · CPC title

• H10D10/231 Primary

  Tunnel BJTs · CPC title