Dynamically compensating for degradation of a non-volatile memory device

Patent metadata

Field	Value
Publication number	US-9418000-B2
Application number	US-201414579971-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 22, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.

First claim

The invention claimed is:

1. An electronic device, comprising:
at least one processor; and
at least one storage device comprising a nonvolatile memory; and
a controller coupled to the memory and comprising logic to:
monitor at least one performance parameter of a nonvolatile memory;
determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory; and
in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory selected from the group consisting of increasing an erase voltage threshold for the nonvolatile memory, increasing a program voltage threshold for the nonvolatile memory, increasing an erase start voltage for the nonvolatile memory, increasing a program start voltage for the nonvolatile memory, modify a seeding voltage for the nonvolatile memory, modifying a true-erase voltage (TEV), modifying an erase pulse timing (TE), and modifying a select gate voltage.

2. The electronic device of claim 1 , wherein the at least one performance parameter comprises at least one of:
a number of program/erase cycles executed on the nonvolatile memory;
a write time parameter for executing write operations on the nonvolatile memory; or
a read failure parameter for read operations on the nonvolatile memory.

3. The electronic device of claim 2 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase voltage threshold for the nonvolatile memory.

4. The electronic device of claim 2 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program voltage threshold for the nonvolatile memory.

5. The electronic device of claim 2 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase start voltage for the nonvolatile memory.

6. The electronic device of claim 2 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program start voltage for the nonvolatile memory.

7. The electronic device of claim 2 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to modify at least one of:
a seeding voltage for the nonvolatile memory;
a true-erase voltage (TEV);
an erase pulse timing (TE); or
a select gate voltage.

8. A storage device, comprising:
a nonvolatile memory; and
a controller coupled to the memory and comprising logic to:
monitor at least one performance parameter of a nonvolatile memory;
determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory; and
in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory selected from the group consisting of increasing an erase voltage threshold for the nonvolatile memory, increasing a program voltage threshold for the nonvolatile memory, increasing an erase start voltage for the nonvolatile memory, increasing a program start voltage for the nonvolatile memory, modify a seeding voltage for the nonvolatile memory, modifying a true-erase voltage (TEV), modifying an erase pulse timing (TE), and modifying a select gate voltage.

9. The storage device of claim 8 , wherein the at least one performance parameter comprises at least one of:
a number of program/erase cycles executed on the nonvolatile memory;
a write time parameter for executing write operations on the nonvolatile memory; or
a read failure parameter for read operations on the nonvolatile memory.

10. The storage device of claim 9 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase voltage threshold for the nonvolatile memory.

11. The storage device of claim 9 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program voltage threshold for the nonvolatile memory.

12. The storage device of claim 9 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase start voltage threshold for the nonvolatile memory.

13. The storage device of claim 9 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program start voltage threshold for the nonvolatile memory.

14. The storage device of claim 9 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to modify at least one of:
a seeding voltage for the nonvolatile memory device;
a true-erase voltage (TEV);
an erase pulse timing (TE); or
a select gate voltage.

15. A controller comprising logic, at least partially including hardware logic, to:
monitor at least one performance parameter of a nonvolatile memory;
determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory; and
in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory selected from the group consisting of increasing an erase voltage threshold for the nonvolatile memory, increasing a program voltage threshold for the nonvolatile memory, increasing an erase start voltage for the nonvolatile memory, increasing a program start voltage for the nonvolatile memory, modify a seeding voltage for the nonvolatile memory, modifying a true-erase voltage (TEV), modifying an erase pulse timing (TE), and modifying a select gate voltage.

16. The controller of claim 15 , wherein the at least one performance parameter comprises at least one of:
a number of program/erase cycles executed on the nonvolatile memory;
a write time parameter for executing write operations on the nonvolatile memory; or
a read failure parameter for read operations on the nonvolatile memory.

17. The controller of claim 16 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase voltage threshold for the nonvolatile memory.

18. The controller of claim 16 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program voltage threshold for the nonvolatile memory.

19. The controller of claim 16 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase an erase start voltage for the nonvolatile memory.

20. The controller of claim 16 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to increase a program start voltage for the nonvolatile memory.

21. The controller of claim 16 , wherein the logic to modify at least one operational attribute of the nonvolatile memory further comprises logic to modify at least one of:
a seeding voltage for the nonvolatile memory device;
a true-erase voltage (TEV);
an erase pulse timing (TE); or
a select gate voltage.

Assignees

• Intel Corp

Inventors

• Raghunathan Shyam Sunder
• Chao Iwen
• Guo Xin
• Kalavade Pranav
• Parat Krishna K
• Zhu Feng

Classifications

• G06F11/1084

  Degraded mode, e.g. caused by single or multiple storage removals or disk failures · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G11C16/32

  Timing circuits · CPC title