Program VT spread folding for NAND flash memory programming

Patent metadata

Field	Value
Publication number	US-9099183-B2
Application number	US-201314139219-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	Aug 4, 2015
Grant date	Aug 4, 2015

Abstract

Embodiments of methods and systems disclosed herein provide a NAND cell programming technique that results in a substantially reduced T prog to complete a programming operation. In particular, embodiments of the subject matter disclosed herein utilize two V pgm programming pulses during each programming iteration, or loop. One of the two programming pulses corresponds to a conventional programming V pgm pulse and the second pulse comprises a programming pulse that having a greater V pgm that is greater than the conventional programming V pgm so that the slow cells are programmed to PV in fewer pulses (iterations), thereby effectively simultaneously programming and verifying cells having different programming speeds.

First claim

The invention claimed is:

1. A method to program a NAND device, the method comprising:
applying a first programming pulse to gates of a plurality of NAND cells of a word line;
determining a programmed threshold voltage (V t ) of each of the plurality of NAND cells in response to the first programming pulse;
categorizing a NAND cell as a fast cell if the determined V t of the NAND cell is greater a first predetermined voltage, otherwise categorizing the NAND cell as a slow cell;
applying a second programming pulse to the gates of the slow-cell NAND cells if a slow cell NAND cell has a determined V t that is less than a program verify (PV) voltage;
applying a third programming pulse to the gates of the slow-cell and fast-cell NAND cells if a NAND cell has a determined V t that is less that the PV voltage, the third programming pulse having a programming voltage that is less than the programming voltage of the second programming pulse; and
repeating the applying of the second and third programming pulses to the gates of the NAND cells until all of the NAND cells have a V t that is greater than the PV voltage.

2. The method according to claim 1 , wherein the determining the programmed threshold voltage (V t ) of each of the plurality of NAND cells comprises applying a special verify pulse to the gates of each of the plurality of NAND cells.

3. The method according to claim 2 , wherein a programming voltage of the second programming pulse is greater than the programming voltage of the third programming pulse by about a difference between the PV voltage and a voltage of the special verify pulse.

4. The method according to claim 3 , wherein the PV voltage is about 1000 mV and the voltage of the special verify pulse is about −1000 mV.

5. The method according to claim 1 , wherein categorizing a NAND cell as a fast cell if the determined V t of the NAND cell is greater a first predetermined voltage, otherwise categorizing the NAND cell as a slow cell further comprises categorizing the NAND cell as a fast cell if the determined V t of the NAND cell is greater or equal to a first predetermined voltage, otherwise categorizing the NAND cell as a slow cell.

6. The method according to claim 1 , wherein the NAND device comprises part of a solid-state memory array or a solid-state drive.

7. A method to program a NAND device, the method comprising:
applying a first programming pulse to the gates of a plurality of NAND cells of a word line;
determining a programmed threshold voltage (V t ) of each of the plurality of NAND cells in response to the first programming pulse;
categorizing a NAND cell as a fast cell if the determined V t of the NAND cell is greater a first predetermined voltage;
categorizing a NAND cell as a middle cell if the determined V t of the NAND cell is less than the first predetermined voltage and greater than a second predetermined voltage;
categorizing a NAND cell as a slow cell if the determined V t of the NAND cell is less than the second predetermined voltage;
applying a second programming pulse to the gates of the slow-cell NAND cells if a slow cell NAND cell has a determined V t that is less than a program verify (PV) voltage;
applying a third programming pulse to the gates of a slow-cell and middle-cell NAND cells if a slow cell NAND cell has a determined V t that is less than a program verify (PV) voltage, the third programming pulse having a programming voltage that is less than the programming voltage of the second programming pulse;
applying a fourth programming pulse to the gates of the slow-cell, middle cell and fast-cell NAND cells if a NAND cell has a determined V t that is less that the PV voltage, the fourth programming pulse having a programming voltage that is less than the programming voltage of the third programming pulse; and
repeating the applying of the second, third and fourth programming pulses to the gates of the NAND cells until all of the NAND cells have a V t that is greater than the PV voltage.

8. The method according to claim 7 , wherein determining the programmed threshold voltage (V t ) of each of the plurality of NAND cells comprises applying a special verify pulse to the gates of each of the plurality of NAND cells.

9. The method according to claim 7 , wherein a programming voltage of the second programming pulse is greater than the programming voltage of the third programming pulse by about a difference between a different between PV voltage and the second predetermined voltage and a different between PV voltage and the first predetermined voltage, and
wherein a programming voltage of the third programming pulse is greater than the programming voltage of the fourth programming pulse by about a different between PV voltage and the first predetermined voltage.

10. The method according to claim 7 , wherein the NAND device comprises part of a solid-state memory array or a solid-state drive.

11. A solid-state memory device, comprising:
an array of a plurality of NAND cells, the array comprising at least one word line coupled to a first plurality of NAND cells of the array;
a read/write circuitry coupled to the array; and
a controller coupled to the read/write circuitry, the controller to control the read/write circuitry to apply a first programming pulse to gates of a plurality of NAND cells of the at least one word line, to determine a programmed threshold voltage (V t ) of each of the plurality of NAND cells in response to the first programming pulse, categorize a NAND cell as a fast cell if the determined V t of the NAND cell is greater a first predetermined voltage, otherwise to categorize the NAND cell as a slow cell, to apply a second programming pulse to the gates of the slow-cell NAND cells if a slow cell NAND cell has a determined V t that is less than a program verify (PV) voltage, to apply a third programming pulse to the gates of the slow-cell and fast-cell NAND cells if a NAND cell has a determined V t that is less that the PV voltage, the third programming pulse having a programming voltage that is less than the programming voltage of the second programming pulse, and to repeat the applying of the second and third programming pulses to the gates of the NAND cells until all of the NAND cells have a V t that is greater than the PV voltage.

12. The solid-state memory device according to claim 11 , wherein the controller is to further determine the programmed threshold voltage (V t ) of each of the plurality of NAND cells by applying a special verify pulse to the gates of each of the plurality of NAND cells.

13. The solid-state memory device according to claim 12 , wherein a programming voltage of the second programming pulse is greater than the programming voltage of the third programming pulse by about a difference between the PF voltage and a voltage of the special verify pulse.

14. The solid-state memory device according to claim 13 , wherein the PV voltage is about 1000 mV and the voltage of the special verify pulse is about −1000 mV.

15. The solid-state memory device according to claim 11 , wherein the controller is to further categorize the NAND cell as a fast cell if the determined V t of the NAND cell is greater or equal to a first predetermined voltage, otherwise categorizing the NAND cell as a slow cell.

16. An electronic system, comprising:
a processor; and
a memory device coupled to the processor, the memory device comprising:
an array of a plurality of NAND cells, the array comprising at least one word line coupled to a first plurality of NAND cells of the array;
a read/write circuitry coupled to the array;

Assignees

• Intel Corp

Inventors

• Srinivasan Charan
• Kalavade Pranav
• Raghunathan Shyam Sunder
• Parat Krishna K

Classifications

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C11/5642 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/3454

  Arrangements for verifying correct programming or for detecting overprogrammed cells · CPC title

• G11C16/107 Primary

  Programming all cells in an array, sector or block to the same state prior to flash erasing · CPC title