NAND memory management

US8943385B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-8943385-B2
Application numberUS-201213658449-A
CountryUS
Kind codeB2
Filing dateOct 23, 2012
Priority dateOct 23, 2012
Publication dateJan 27, 2015
Grant dateJan 27, 2015

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Abstract

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Apparatus, systems, and methods to manage NAND memory are described. In one embodiment, a memory controller logic is configured to apply a binary parity check code to a binary string and convert the binary string to a ternary string.

First claim

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The invention claimed is: 1. An apparatus comprising: a memory controller logic to: apply a binary parity check code to a binary string; and convert the binary string to a ternary string determine, for each ternary combination in a set of 2187 ternary combinations, a number of neighbors which have a hamming distance of 1 from the ternary combination; order the set of 2187 ternary combinations in ascending order of the number of neighbors which having a hamming distance of 1…

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What does patent US8943385B2 cover?
Apparatus, systems, and methods to manage NAND memory are described. In one embodiment, a memory controller logic is configured to apply a binary parity check code to a binary string and convert the binary string to a ternary string.
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F11/1072. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 27 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).